Design of Advanced STA

To Study the impact of LOCV and

CPPR on timing QOR

Ayush Singhal
Kurian Abraham
Sandesh V S
What we want to achieve!!

PERT with sequential elements

Location based AOCV ??

Clock Path Pessimism Removal
DFF (CPPR)

Launch Path
Capture Path
Common Point
What we want to achieve!!
DFF

Implement an STA engine

PERT with sequential elements
Clock Path Pessimism
Implement
Removalan STA
(CPPR)
Launch Path
engine
Location based AOCV Capture Path
Common Point
sequential elements
CPPR
LOCV

Compare the timing results with/without LOCV/CPPR

Method to generate the depth and distance based
AOCV derate table (WIP)
How to handle LOCV?
Derate = f(depth, distance)Primary Input Primary Output
Block 2
Objective: Understand how to
partition adjacency list into
independent blocks to get the
correct location based derate
value
Objective: Understand how to
partition adjacency list into
Comb Gate unconnected blocks to get the
correct location based derate
value
Sequential Elements Break the
Primary Input & Primary Outp

Block 3
Block 1
I/P to Flop Flop to Flop to O/P
Flop

Graph Partition Connected Component Analysis

(CCA) Get the bounding box information using
CCA (Adjacency List ) Block 1, 2, 3 Virtuoso Skill
Find all nodesHow To are
which handle clock network
connected and put?? Compute the depth and distance and then
them
in one block calculate the derate

Block 1: F1, F2, In1, N1,

Result - LOCV vs OCV Setup Time Objective: Why LOCV!!

Derate with path length for long path Depth vs O/P Arrival time for different STA conf.
OCV LOCV Only depth based OCV OCV LOCV Onl y depth ba s ed OCV
1.16 3
Less Path delay
Less pessimistic
1.14 2.5
Easy to meet setup
constraint
Decrease in

Arrival Time (ns)

1.12 2
Derate Value

derate

1.1 1.5

1.08 1

1.06 0.5

1.04 0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47

Stage / Depth Stage / Depth

Setup Time
Result - LOCV vs OCV Hold Time

Derate with path length for Short path Arrival time (Short path) for different configuration
OCV LOCV Depth bas ed LOCV OCV LOCV Depth based LOCV

0.94 0.16

0.14 More Path delay

Less pessimistic
0.92
0.12 Easy to meet hold
constraint

Arrival Time (ns)

Derate Value

0.1
0.9

0.08
Increase in derate
0.88
0.06

0.04
0.86

0.02

0.84 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Stage / Depth Stage / Depth

Hold Time
Finding the Lowest Common Ancestor (LCA)

Objective: CPPR point between two nodes Use

LCA Algorithm
Understand algorithm for lowest common
ancestor(LCA)
 Finding the Lowest Common Ancestor (LCA)

Objective: CPPR point between two nodes

Understand algorithm for lowest common ancestor(LCA)
Step 2: Find Step 1: DFS TRAVERSAL
minimum node level A AD AD Save node at start time
D Q Q Q
between index 2 and At intermediate time
index 7 CLK CLK CK At finish time
Step 3: CK CLK CK
Min=1 @ index
CLK
3 B4 B7 B10
CPPR = E(3) =
Common point
B2
B3 Save
Save
Save at intermediat
at start
at time
finish
CLK B1 B2 B5 B6 B8 B9 B2
time
time

Index 0 1 2 3 4 5 6 7 8 9 10 FF1/
FF1
FF1 B6
(Time) FF1/
FF1/
FF1/ FF2/ FF3/
FF3/ CK
/CK
/CK
Table1 CLK B2 B6 B6 B6 B2 CLK
Node B2
CK
CK
CK B CK CK
CK
CK
visited 2
E(i)
Index 0 1 2 3 4 5 6 7 8 9 10
-Time FF2/ FF3/
FF3
FF3
2 1
Table2 Node
0 1 2 11 2
3 3
3 22 3 0 CK CK
/CK
/CK
level
L(i)
CPPR Point (Common Path Pessimism Removal)

Objective:
2 Types of CPPR Points in a design:
Understand what does CPPR point means in context with
Capture Flip Flop and launch
LOCV.
Flop
And how to find the CPPR point(s) for a block??
For the Block

Longest Path L1

CPPR during Setup check:

C PPR
- Merge point
For capture flop (F4) Find the Launch
SETUP

Shortest Path S1
Flop with longest path (F1).
Then find the CPPR between 2 flops (LCA)
CPPR - HOLD CPPRSetup
CPPR during Hold check:
CPPR - HOLD CPPRHold For capture flop (F4) Find the Launch
Flop with smallest path (F2).
CPPR - SETUP CPPRSetup Then find the CPPR between 2 flops (LCA)
CPPRHold
CPPR Point (Common Path Pessimism Removal)

2 CPPR Points:
Capture Flip Flop
For the Block

Objective:
Understand what does CPPR point means in
context with LOCV.
What does CPPR of a block signify?
And how to find the CPPR point for a block??

B3

Block 2
CPPR point for a block Point from where
clock start diverging for a block
 CPPR Point (Common Path Pessimism Removal)

2 CPPR Points: Step 1: Trace back the starting point:

Capture Flip Flop Topological Traversal
For the Block i.e. capture flop is getting input/data from which
all launch flop(s)
Starting_flop (F3) F1
Starting_flop
Starting_flop(F3) = F1(F4) F1, F2

Starting_flop(F4) = F1, F2

Step 2: Find CPPR point between Capture and Step 3: Find CPPR point between all CPPR point
it associated launch flops
Now we have complete block with all the
found in step 2
CPPR(F3, F1) B4 combinational gates
CPPR(B4, B3, B1)and
B1also the elements in
Step 4: Add buffer(s)
the in pathpath
clock B1 to B4
CPPR(F4, F1) into the Block 1
B3
CPPR(F4, F2) Block 1: F1, F2, In1, N1, F3, F4
B1 + B2 + B3 + B4
STA on Clock Network

Objective: Understand how to handle clock network in case of LOCV

2) Recalculate
1) Topological arrival from CPPR
traversal point
using with derate
global AOCV derate values
values
Perform STA on clock network
starting from the CLK port

Calculate arrival time (GAT) at

each node
Determine CPPR point for each
LOCV block

A Recalculate AT for all the nodes

GATCPPR(block1) GATCPPR(block2)
after the CPPR point of each
CLK
B

block
C

Calculate GAT and

AT for max and min
GAT(n)= =AT(n-1)
AT(n) GAT(n-1) + delay_gate(n)
+ delay_gate(n) * global_derate
* AOCV_derate
analysis
n=0 -> AT(n-1) = GATCPPR
Result - CPPR vs Non CPPR STA Objective: How does CPPR
help??
Bar graph for C PPR vs N O N -C PPR STA - H old
Bar graph for CPPR vs NON-CPPR STA - Setup
XI500

XI105
Setup slack
become less XI9

-ve XI765

XI8

XI180 -0.97 -0.13

-1.06 -0.22
XI179
-0.92 -0.21
Setup Slack (ns) > 0 Pass XI148 Hold Slack (ns) > 0 Pass -1.24 -0.16
-1.17 -0.16
XI149 -0.69 -0.25
-2 -1.5 -1 -0.5 0 0.5 -0.68 -0.24
-0.69 -0.32
Setup Slack (ns) -0.68 -0.31
-3 -2.5 -2 -1.5 -1 -0.5 0
CPPR = False CPPR = True
Hold Slack (ns)
Clock_Pessimism CPPR = False
Using CPPR, slack for all these paths > 0
Pass
When no CPPR, slack < 0 Fail
Road Map

Developing a method to calculate the derate factor based on

depth and distance.
Varying the length spatially and Vth as a random variable
HSPICE Montecarlo to find variation in output arrival
time

Testing STA engine for few other netlist and comparing the
results

Final Report
Depth for the block

Objective: Understand the 2 Types of Depth:

how to calculate the depth of Simple Depth (d)
a gate in a path Combined Depth (dc): Includes clock path
depth also
Derate with path length for long path
dc = 5 + 1 or Start with d OCV LOCV
=1 Simple-Depth-based-Dis-AOCV
1.16
dc=6 || d=1 dc=7 dc=8 dc=9 dc=10
1.15
d=2 d=3 d=4 d=5
Due to depth = 1, derate value
@Merging Point
dc=11 (Max) 1.14 increased
dc=8 (Min)

Derate Value
dc=6 || d=1 dc=7 dc=8
1.13

d=2 d=3 d=5 (Max)

d=3 (Min) 1.12

1.11
d=5 d=4 d=3 d=2 d=1 Max and Min 1.1
depth to cal the
derate value 1.09

1.08
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47

Stage / Depth
Though there was not much difference in hold
or setup slack. Skip
 STA engine Architecture Objective: Summarize the entire
flow.

Adjacency_li Design_cons
Gate cap NETLIST
Step st
(.txt) (.csv) s
Topo trav for clock tree 6
Adjacency List 1
Derate
Adjacency_lis Primary Conn_Block (.csv)
(Bbox) SLEW (.csv)
t Input
Connected comp analysis
Conn 2 Topo Trav for each block Delay (.csv)Design_cons 7
block (AOCV based delay at clock pin of flop +
Topo trav on the comb path of the block)
Adjacency_lis
t Max and MIN
Topo Traversal to determine input 3 CPPR point
corresponding to every output Design_cons
Hold and Setup check 8
Adjacency_list - update
Conn_ip_flops, conn_ip Setup and Hold
slack
Summary and Detailed Report
Lowest Common Ancestor 4 Generation
(Prepare tables) 9
euler_le euler_node_na euler_m
vel me ap
Conn_Block Find CPPR point for each block Blocks for Summary Report Detailed Report
skill Skill
Adjacency_list and update the block with clock Bounding engine 5
path box

Conn_Block

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