EE

EE 587
587
SoC
SoC Design
Design &
& Test
Test

Partha Pande
School of EECS
Washington State
University
pande@eecs.wsu.edu
 Test
Test Methodologies,
Methodologies, and
and Yield
Yield

Reference: Essentials of Electronic Testing by

Bushnell and Agrawal
 Introduction
Introduction

VLSI realization process

Verification and test
Ideal and real tests
Costs of testing
 VLSI
VLSI Realization
Realization Process
Process
Customers need

Determine requirements

Write specifications

Design synthesis and Verification

Test development
Fabrication
Manufacturing test

Chips to customer
 Definitions
Definitions

Design synthesis: Given an I/O function, develop

a procedure to manufacture a device using
known materials and processes.
Verification: Predictive analysis to ensure that
the synthesized design, when manufactured, will
perform the given I/O function.
Test: A manufacturing step that ensures that the
physical device, manufactured from the
synthesized design, has no manufacturing
defect.
 Verification
Verification vs.
vs. Test
Test
Verifies correctness of Verifies correctness of
design. manufactured hardware.
Performed by Two-part process:
simulation, hardware 1. Test generation: software
emulation, or formal process executed once
methods. during design
Performed once prior 2. Test application: electrical
to manufacturing. tests applied to hardware
Responsible for quality Test application performed on
of design. every manufactured device.
Responsible for quality of
devices.
 Problems
Problems of
of Ideal
Ideal Tests
Tests

Ideal tests detect all defects produced in

the manufacturing process.
Ideal tests pass all functionally good
devices.
Very large numbers and varieties of
possible defects need to be tested.
Difficult to generate tests for some real
defects. Defect-oriented testing is an open
problem.
 Defect
Defect vs.
vs. Fault
Fault

To become a fault, the defect needs to

connect two disjoint conductors or
disconnect a continuous pattern
 Wafer
Wafer Defect
Defect Map
Map

Faults are a percentage of defects

Same distribution with fewer points
 Real
Real Tests
Tests

Based on analyzable fault models, which

may not map on real defects.
Incomplete coverage of modeled faults due
to high complexity.
Some good chips are rejected. The
fraction (or percentage) of such chips is
called the yield loss.
Some bad chips pass tests. The fraction
(or percentage) of bad chips among all
passing chips is called the defect level.
 Testing
Testing as
as Filter
Filter Process
Process

Good chips Prob(pass test) = high Mostly

good
Prob (good) = y Pr ow
ob l chips
(fa ) =
il est
Fabricated tt
s es
chips as t)
( p =
b lo
r o w
P
Defective chips Mostly
bad
Prob(bad) = 1- y Prob(fail test) = high chips
 Costs
Costs of
of Testing
Testing
Design for testability (DFT)
Chip area overhead and yield reduction
Performance overhead
Software processes of test
Test generation and fault simulation
Test programming and debugging
Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost
 Design
Design for
for Testability
Testability (DFT)
(DFT)
DFT refers to hardware design styles or added
hardware that reduces test generation complexity.
Motivation: Test generation complexity increases
exponentially with the size of the circuit.
Example: Test hardware applies tests to blocks A
and B and to internal bus; avoids test generation
for combined A and B blocks.
Int.
Logic bus Logic
PI PO
block A block B

Test Test
input output
 Present
Present and
and Future*
Future*

1997 -2001 2003 - 2006

Feature size (micron) 0.25 - 0.15 0.13 - 0.10
Transistors/sq. cm 4 - 10M 18 - 39M
Pin count 100 - 900 160 - 1475
Clock rate (MHz) 200 - 730 530 - 1100
Power (Watts) 1.2 - 61 2 - 96

* SIA Roadmap, IEEE Spectrum, July 1999

Cost
Cost of
of Manufacturing
Manufacturing Testing
Testing in
in
2000AD
2000AD
0.5-1.0GHz, analog instruments,1,024
digital pins: ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M
Running cost (five-year linear depreciation)
= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/year
Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second
 Roles
Roles of
of Testing
Testing

Detection: Determination whether or not the

device under test (DUT) has some fault.
Diagnosis: Identification of a specific fault
that is present on DUT.
Device characterization: Determination and
correction of errors in design and/or test
procedure.
Failure mode analysis (FMA): Determination
of manufacturing process errors that may
have caused defects on the DUT.
Yield
Yield Analysis
Analysis &
& Product
Product Quality
Quality

Yield and manufacturing cost

Clustered defect yield formula
Yield improvement
Defect level
Test data analysis
Example: SEMATECH chip
Summary
 VLSI
VLSI Chip
Chip Yield
Yield
A manufacturing defect is a finite chip area
with electrically malfunctioning circuitry
caused by errors in the fabrication process.
A chip with no manufacturing defect is called
a good chip.
Fraction (or percentage) of good chips
produced in a manufacturing process is called
the yield. Yield is denoted by symbol Y.
Cost of a chip:

Cost of fabricating and testing a wafer

--------------------------------------------------------------------
Yield x Number of chip sites on the wafer
 Clustered
Clustered VLSI
VLSI Defects
Defects

Good chips
Faulty chips

Defects
Wafer
Unclustered defects Clustered defects (VLSI)
Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77
 Yield
Yield Parameters
Parameters
Defect density (d ) = Average number of
defects per unit of chip area
Chip area (A)
Clustering parameter ()
Negative binomial distribution of defects,
p (x ) = Prob (number of defects on a chip = x )
(+x ) (Ad /) x
= ------------- . ----------------------
x ! () (1+Ad /) +x
where is the gamma function
=0, p (x ) is a delta function (max. clustering)
= , p (x ) is Poisson distr. (no clustering)
 Yield
Yield Equation
Equation

Y = Prob ( zero defect on a chip ) = p (0)

Y = ( 1 + Ad / )

Example: Ad = 1.0, = 0.5, Y = 0.58

Unclustered defects: = , Y = e - Ad
Example: Ad = 1.0, = , Y = 0.37
too pessimistic !
 Defect
Defect Level
Level or
or Reject
Reject Ratio
Ratio

Defect level (DL) is the ratio of faulty

chips among the chips that pass tests.
DL is measured as parts per million (ppm).
DL is a measure of the effectiveness of
tests.
DL is a quantitative measure of the
manufactured product quality. For
commercial VLSI chips a DL greater than
500 ppm is considered unacceptable.
 Determination
Determination of
of DL
DL

From field return data: Chips failing in the

field are returned to the manufacturer. The
number of returned chips normalized to
one million chips shipped is the DL.
From test data: Fault coverage of tests and
chip fallout rate are analyzed. A modified
yield model is fitted to the fallout data to
estimate the DL.
 Modified
Modified Yield
Yield Equation
Equation
Three parameters:
Fault density, f = average number of
stuck-at faults per unit chip area
Fault clustering parameter,
Stuck-at fault coverage, T
The modified yield equation:

Y (T ) = (1 + TAf / ) -
Assuming that tests with 100% fault coverage
(T =1.0) remove all faulty chips,
-
Y = Y (1) = (1 + Af / )
 Defect
Defect Level
Level
Y (T ) - Y (1)
DL (T ) = --------------------
Y (T )

( + TAf )
= 1 - --------------------

( + Af )
Where T is the fault coverage of tests,
Af is the average number of faults on the
chip of area A, is the fault clustering
parameter. Af and are determined by
test data analysis.
 Test
Test Coverage
Coverage from
from Fault
Fault
Simulator
Simulator
Stuck-at fault coverage

Vector number
 Measured
Measured Chip
Chip Fallout
Fallout
Measured chip fallout

Vector number
 Model
Model Fitting
Fitting
Chip fallout vs. fault coverage
Chip fallout and computed 1-Y (T )

Y (1) = 0.7623

Measured chip fallout

Y (T ) for Af = 2.1 and = 0.083

Stuck-at fault coverage, T

 Computed
Computed DL
DL

237,700 ppm (Y = 76.23%)

Defect level in ppm

Stuck-at fault coverage (%)

 Summary
Summary
VLSI yield depends on two process parameters,
defect density (d ) and clustering parameter ()
Yield drops as chip area increases; low yield
means high cost
Fault coverage measures the test quality
Defect level (DL) or reject ratio is a measure of
chip quality
DL can be determined by an analysis of test
data
For high quality: DL < 500 ppm, fault coverage
~ 99%