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Chapter #6 - Intro To HDL
Chapter #6 - Intro To HDL
Chapter #6 - Intro To HDL
Outline
Verilog Expressions
Primitives Gates
2
What is Verilog?
Verilog is a HDL (Hardware Description Language) use to design a digital
system.
VHDL is another hardware description language used.
3
What is Verilog?
IEEE 1364-2001 is the latest Verilog HDL standard.
Verilog is case sensitive (Keywords are in lowercase).
4
Differences between Verilog and VHDL
Verilog is similar to C- language.
VHDL is similar to ADA (a structured, statically typed, imperative, wide-
spectrum, and object-oriented high-level computer programming language,
5
Verilog-logic Values
0 zero, logic low, false, ground
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Types Verilog Coding
Behavioral
Procedural code, similar to C programming
Little structural detail (except module interconnect)
7
Verilog Keywords
Note : All keywords are defined in lower case
Examples :
module, endmodule
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Module Declaration
Module Declaration:
endmodule
test
in1 out1
out2 module test(out1, .., inN);
in2
.. // declarations
f
endmodule
inN outM
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Exercise #1
Consider a full adder block below:
A B
CO S
module full_adder(A,B,Cin,Co,S);
[content]
endmodule
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Input Declaration
Two types of representation:
A B
Scalar
Full Adder
input list of input identifiers;
Example: input[7:0]D,[3:0]S,EN; D3
D2
D1
D0
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Exercise #2
Include the inputs for the full adder:
A B
Full Adder
CO S
module full_adder(A,B,Cin,Co,S);
input A,B,Cin;
CO S
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Exercise #3
Now, include the output declaration for the full adder:
A B
CO S
module full_adder(A,B,Cin,Co,S);
input A,B,Cin;
output Co,S;
Do not forget the
[content] semicolon!
endmodule
15
Elements in Verilog
Nets
Nets are physical connections between devices
Many types of nets, but all we care about is wire.
Example
wire [2:1]w;
or
wire w1,w2;
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Elements in Verilog
Registers
Implicit storage-holds its value until a new value available.
Usually registers are also the circuits output.
Register type is denoted by reg.
Multiple line:
/* This is a multiple line
Nest multi-line
*/
18
Numbers Declaration in Verilog
Numbers (all number systems) can be declared by using the following
command:
<size><radix><value>
19
Verilog Primitives
Basic logic gates only:
and
or
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Primitive Gates
Let say we have an AND gate:
g1
and g1(x,A,B);
endmodule
21
Continuous Assignments
We still defining AND gate but with equation type of approach:
g1
endmodule
23
Verilog Operators
24
25
a = 4b1010;
b = 4b1100;
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Given:
b = 2b11;
a = 4b1010;
Bitwise Operations
c = a ^ b;
27
A
S
Co
Write a Verilog code for the circuit in primitives gate as well as in continuous
assignment.
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Exercise #4: Primitives Gate
module half_adder(A,B,S,Co);
A
Co
xor g1(S,A,B);
and g2(Co,A,B);
endmodule
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Exercise #4: Continuous Assignment
module half_adder(A,B,S,Co);
Co
assign S = A ^ B;
assign Co = A & B;
endmodule
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Exercise #5
Lets consider the following circuit:
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Exercise #5: Primitives Gate
and g1(e,A,B);
not g2(y,C);
or g3(x,e,y);
endmodule
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Exercise #5: Continuous Assignment
assign x = (A&B)|(~C);
assign y = ~C;
endmodule
33
Exercise #6
Lets consider the full adder circuit below, which is made from 2 half adders.
34
g2
g1
w2
Exercise #6: Primitives Gate
w1
g4
g3
w3
g5
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w1
module full-adder(A,B,Cin,Cout,Sum);
g1
g5 input A,B,Cin;
output Cout, Sum;
and g1(w1,A,B);
xor g2(w2,A,B);
and g3(w3,Cin,w2);
xor g4(Sum,w2,Cin);
or g5(Cout,w1,w3);
endmodule
36
Exercise #6: Primitives Gate
But it is also made out of 2 half adder (we already have half-adder module
previously).
w3
HA1 w2
HA2
37
Exercise #6: Primitives Gate
module full-
w1 adder(A,B,Cin,Cout,Sum);
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Exercise #6: Continuous Assignment
module full-adder(A,B,Cin,Cout,Sum);
g1
w1
g5
input A,B,Cin;
endmodule
39
Exercise #7
Now, lets try a little bit complicated circuit. 4-bit adders.
A3 B3 A2 B2 A1 B1 A0 B0
S3 S2 S1 S0
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Exercise #7: Solution (i)
module add4 (S,Cout,A,B,Cin);
input [3:0]A, B; A3 B3 A2 B2 A1 B1 A0 B0
input Cin ;
output [3:0] S : C2 C1 C0 Cin
output Cout ;
endmodule
41
Exercise #7: Solution (ii)
module add4 (S,Cout,A,B,Cin);
input [3:0]A,B; A3 B3 A2 B2 A1 B1 A0 B0
input Cin;
output [3:0]S; C2 C1 C0 Cin
output Cout;
endmodule
42
Exercise #8
Simulate the add4 module according to the sequence of binary values
shown in the table below, and then stop simulation.
43
Exercise #8: solution
timescale 1ns/1ns
A = 4b1010;
module test_add4; B = 4b0101;
reg [3:0]A,B; Cin = 1b0;
reg Cin; #10;
44
if-else Statement
Format
if (conditional_expression) statement;
else statement;
45
Exercise #9: 2-to-1 Mux
The same 2-to-1 multiplexer:
s f
0 w0
w1
endmodule
46
Exercise #10: 4-to-1 Mux
module mux4to1 (w0, w1, w2, w3, S, f);
input w0, w1, w2, w3; s1 s0 f
input [1:0]S;
output f; 0 0 w0
endmodule
47
Case Statement
Format
case(expression)
1) Many possible alternatives
alternative1: statement;
48
Exercise #11: 4-to-1 Mux
module mux4to1 (W, S, f);
input [0:3] W; s1 s0 f
input [1:0] S;
output f; 0 0 w0
endmodule
49
Exercise #12: 2-to-4 Decoder
module dec2to4 (W, Y, En);
input [1:0]W;
input En; En w1 w0 y0 y1 y2 y3
output [0:3]Y;
1 0 0 1 0 0 0
endmodule
50
Exercise #13: 2-to-4 Decoder
module dec2to4 (W, Y, En);
input [1:0] W;
input En;
output [0:3] Y; En w1 w0 y0 y1 y2 y3
reg [0:3] Y;
1 0 0 1 0 0 0
endmodule 51
Exercise #14: 7-Segment Decoder
module seg7 (bcd, leds);
input [3:0] bcd;
output [1:7] leds;
reg [1:7] leds;
52