Professional Documents
Culture Documents
Delay Time Estimation in Digital Design
Delay Time Estimation in Digital Design
Delay Time Estimation in Digital Design
In most CMOS circuits the delay of The delay of simple gates maybe
a single gate is dominated by the approximated by constructing an
rate at which the output node can equivalent inverter. WHY?
be charged and discharged.
Consider a 3 input NOR gate with
The delay can be approximated by:
Wp = Wn for all transistors:
tdr = tr/2 and tdf = tf/2
When there is a path in the pull-up
The average delay for rising and network from the output to VDD
falling output transitions is: the effective gain factor of the
tav = (tdf+tdr)/2 series p-type transistors is:
The delay equations presented use 1
only first order MOS equations for eff
1 1 1
the calculations of drain currents p1 p2 p3
and thus do not account for second
order effects.
2
Gate Delays
For the pull-down network only The gain factor of the three series
one n-type transistor need to be p-type transistors is given by:
on in order for us to have a path p
series
from the output node to ground. 3
eff =n and this gain factor is The delay through this series
improved by a factor of three if connection is therefore given by:
all the n-type devices conduct CL
series k
simultaneously. p
VDD
For the NOR gate example we 3
can thus estimate the rise and fall If all three parallel n-type devices
times as follows: are conducting we have that:
tf
tr k
CL
and t f k
CL tf
p n 3
VDD
3
3
RC Delays
5
RC Delay Model
6
Delay Estimation (RC Models)
7
The Elmore Delay Model
Vin
R1 R2 R3 RN
C2
The Elmore delay estimates
C1 C
the delayCof an RC ladder as
3
N
8
AND Gate Intrinsic Capacitance
9
Two Input NAND Gate
10
CMOS-Gate Transistor Sizing
It has been shown that to have If Wp = 2Wn the delay response for
symmetric switching in an inverter an inverter pair:
we need to make the width of the tinv _ pair t fall t rise
p-type device (Wp) at least 2->3 tinv _ pair R3Ceq 2
R
3Ceq
times that of the n-type device 2
tinv _ pair 6 RC eq
(Wn).
This approach increases the area The above expression can be
occupied by the p-type devices and compared to one for equal sized
dynamic power dissipation. inverter devices. The inverter pair
delay becomes:
Some structures can be cascaded to
use minimum or equal sized tinv _ pair t fall t rise
devices without compromising the tinv _ pair R 2Ceq 2 R 2Ceq
switching response. tinv _ pair 6 RC eq
11
Stage Ratio
12