Low Power CMOS Design

Design and Analysis of

Inverter Chain and 2:1 Mux
using PTL and TG Logic

Sahil Malhotra 104642647

 Contents
Introduction
Size of PMOS and NMOS
Delays
Circuit
Simulation
Simulation Results
Mux using TG Logic
Mux using PTL Logic
 Introduction

No gate can switch instantaneously

Voltage Swing
Inverter Chain
High Input Resistance
No Static Power Consumption
 Sizing of PMOS and NMOS

External Capacitance
Internal Capacitance
Number of Stages N=Ln F/Ln f
PMOS to NMOS W/L Ratio is taken as 2:1
DELAY
Circuit for Single Inverter
Circuit for 5 Stage Inverter
Chain
Transistor Sizing Table
Transistor Width (m) Length (m)

M23 2 0.18

M25 1 0.18

M24 20 0.18

M27 10 0.18

M25 60 0.18

M28 30 0.18

M29 180 0.18

M30 90 0.18

M31 540 0.18

M32 250 0.18

 Simulation Results
Stages Time Constant(ns) Propagation Delay(ns) Rise time(ns) Fall time
(ns)

1 0.05 0.06 0.095 0.05

2 9 11.5 10 18.5

3 3.9 3.75 6.5 3.15

4 1 1.3 1.1 2.2

5 0.225 0.3 0.45 0.45

Power Consumption
Stages Power (W)

1 12.5

2 500

3 300

4 350

5 400
 2:1 Mux using TG and PTL
Logic
S A B Output

0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
 Transmission Gate Logic
A transmission gate is an electronic
element and good non mechanical relay
built with CMOS technology.
2:1 Mux using TG logic
 Pass Transistor Logic
Reduces the number of transistors
A Mux can be designed using various
logics.
Circuit for Pass Transistor
Logic
 Simulation Results
Logic Power Delay
PTL 260nW 1.6ns
TG 280nW 1.8ns
 References
Ila Gupta, Neha Arora, Prof. B.P. Singh Simulation and analysis of
2:1 Multiplexor circuits using 90nm technology International journal
of modern engineering research Vol1
Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey
S. Gowri Sankar Korla, Kumar Abhishek, Ashutosh Pandey Role of
Chain Inverter to Enhance Power Quality IOSR Journal of Electrical
and Electronics Engineering. July 2012
Wikipedia