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Ch3 PowerBasics
Ch3 PowerBasics
Jan M. Rabaey
Metrics
Dynamic power
Static power
Energy-delay trade-offs
Delay (sec):
Performance metric
Energy (Joule)
Efficiency metric: effort to perform a task
Power (Watt)
Energy consumed per unit time
Power*Delay (Joule)
Mostly a technology parameter measures the efficiency of
performing an operation in a given technology
Energy*Delay = Power*Delay2 (Joule-sec)
Combined performance and energy metric figure of merit of
design style
Other Metrics: Energy-Delayn (Joule-secn)
Increased weight on performance over energy
Pdyn f
with f the switching frequency
Sources:
Charging and discharging capacitors
Temporary glitches (dynamic hazards)
Short-circuit currents
Vdd 2
E01 CLVDD
1 2
PMOS iL ER CLVDD
2
A1 NETWORK
Vout
AN 1 2
CL EC CLVDD
NMOS 2
NETWORK
V VT
dV
E 01 = VC C dt = CV dV C = CV (V VTH )
0 dt 0
CV
T
I
RC
E R I ( RI )dt RI 2T (
0
T
)CV 2
= CLVDD2 f01
= CLVDD2 f P01
= CswitchedVDD2 f
p01
AND (1 - pApB)pApB
OR (1 - pA)(1 - pB)(1 - (1 - pA)(1 - pB))
XOR (1 - (pA +pB 2pApB))(pA + pB 2pApB)
XOR
NAND/NOR
VDD
But:
Reconvergent fanout
Feedback and temporal/spatial correlations
reconvergence
no reconvergence reconvergent
PZ = 1-(1-PA)PB PZ = 1-(1-PA)PA ?
NO!
PZ: probability that Z=1 PZ = 1
Must use conditional probabilities
PZ = 1- PA . P(X|A) = 1
probability that X=1 given that A=1
Becomes complex and intractable real fast
Low Power Design Essentials 2008 3.
Temporal Correlations
Z
Glitch
Gate Delay
3.0
Out6
Out2
2.0
Out6
Voltage (V)
Out8
1.0 Out7
Out1
Out5
Out3
0.0
0 200 400 600
Time (ps)
A,B A,B
C,D C,D
X X
Y Y
Z Z
VDD
V DD -V T
vin
VT
V in I sc V out
I peak t
CL ishort
Psc ~ f
Isc IMAX
Isc ~ 0
Vout Vout
Vin
Vin CL
CL
x 10-4
2.5
1
CL = 500 fF
0.5
-0.5
0 20 40 60
time (s)
Equalizing rise/fall times of input and output signals limits Psc to 10-15%
of the dynamic dissipation
Low Power Design Essentials 2008 [Ref: H. Veendrick, JSSC84] 3.
Modeling Short-Circuit Power
in
C SC k (a b)
out
a, b: technology parameters
k: function of supply and threshold voltages, and transistor sizes
2
E SC C SCVDD
Drain leakage
Diffusion currents
Drain-induced barrier lowering (DIBL)
Junction leakages
Gate-induced drain leakage (GIDL)
Gate leakage
Tunneling currents through thin oxide
d
VM VDD
1 2d
d VDD 1 d
I stack - ( )
1 2 d (instead of the
10 S
expected factor of 2)
I inv
2.5
90 nm NMOS
IM1
Ileak (A)
factor 9
1.5 IM2
1
0.5
Leakage Reduction
0
2 NMOS 9
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
3 NMOS 17
VM (V)
4 NMOS 24
2 PMOS 8
3 PMOS 12
4 PMOS 16
1.8
I Leak
1.6
90 nm CMOS
1.4 I GS
1.2
Igate (A)
0.8
Modeled in BSIM4
Also in BSIM3v3 (but not
0.6
always included in foundry
0.4 models)
0.2 NMOS gate leakage
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
usually worse than
Low Power Design Essentials 2008 VDD (V) PMOS 3.
Other sources of static power dissipation
p+ n+ n+ p+ p+ n+
n well
p substrate
sense amplifiers,
voltage converters
and regulators,
sensors, mixed-signal
components, etc
a switching activity
CL load capacitance IDC static current
CCS short-circuit Ileak leakage current
capacitance
Vswing voltage swing
f frequency
energy
P rate static power
operation
CL
3 15 word
addr
input line
CW CL
-4 -10
x 10 x 10
1 5
0.8 4
Power (W)
0.6
Delay (s)
3
A
0.4 2
0.2 1
B
0 04
4 A
V 3 V 3 B
-0. 4
DD
(V 2
0.4
0 DD
(V 2 0 -0.4
) 1 0.8 (V) ) 1 0.8 0.4 (V)
VT
H
Low Power Design Essentials 2008 [Ref: T. Sakurai and T. Kuroda, numerous references] 3.
The Energy-Delay Space
Equal
energy
curves
VTH
Energy minimum
Low Power Design Essentials 2008 3.
Energy-Delay Product as a Metric
3.5
3
delay 90 nm technology
2.5 VTH approx 0.35V
1.5
1 energy-delay
0.5 energy
0
0.6 0.7 0.8 0.9 1 1.1 1.2
VDD
Emax Pareto-optimal
designs
Emin
Dmin Dmax Delay