CISC v/s RISC

CISC
Increasing complexity of Instruction Set
Single instruction performs a complex sequence
of operations over many clock cycles.
Processors were controlled by Microcode ROMs
(Read Only Memories) that were faster than
main memory.
The microcode ROM absorbed an unreasonable
proportion of the area of a single chip, leaving
little room for other performance- enhancing
features.
 RISC Idea
Data movement instructions account for
almost half of all instructions executed.
Second most frequent are the control flow
instructions.
Pipelining, Cache memory and super-
scalar instruction execution techniques
can be used.
 Pipelines-Steps Of Execution
A processor executes an individual instruction in
a sequence of steps. A typical sequence might
be:
Fetch
Decode
Reg
ALU
Mem
Res
Start the next instr. before the current one has
finished.(pipelining)
 Pipeline Hazards
The result from one instruction is used as
an operand by the next instruction.
Branch instructions result in even worse
pipeline behaviour.
 RISC Architecture
A fixed (32-bit) instruction size with few
formats
A load-store architecture where
instructions that process data operate only
on registers and are separate from
instructions that access memory.
A large register bank all of which could be
used for any purpose, to allow the load-
store architecture to operate efficiently.
 RISC Organization
Hard-wired instruction decode logic
Pipelined execution
Single-cycle execution
 RISC Advantages
A smaller die size
A shorter development time
A higher performance
 RISC Drawbacks
RISCs generally have poor code density
compared with CISCs.
RISCs don't execute x86 code