Sequential Circuits

Inputs Combinational Outputs

circuit Memory
Next elements
state Present
state

Clock
a periodic external event (input)
Clock
Comparision b/w combinational & sequential
logic circuits.
combinational sequential
The output variables are at all times The output variables dependent not
dependent on the combination of only on present input variables but
input variables also depend upon the past
information
Memory unit is not required Memory unit is required to store the
past information
Faster in speed , because the delay Slower than the combinational
b/w input & output is due to circuits
propagation delay of logic gates
These are easy to design These circuits are comparatively
harder to design
It does not have a clock signal It may or may not have a clock
signal . Most sequential circuits
have a clock signal
Eg: Adders , subtractors , MUX, Eg: flip-flops ,counters , shift
DEMUX registers
Classification of sequential logic circuits
(depending on timing of their signals)

Synchronous Asynchronous

The change in input signal can The change in input signal can
effect memory element upon effect memory element at any
activation of clock signal instant of time.

Memory elements are clocked Memory elements are either

flip-flops
The maximum operating
speed of clock depends on
time delays involved
Easier to design
unclocked flip-flops or time
delay elements
Because of absence of clock
asynchronous circuits operate
faster than synchronous
circuits
More difficult to design
Memory elements are either latches or flip-flops.
The main difference b/w latches & flip-flops is in the
method used for changing their state.
Flip-flop is a logic circuit used to store one bit of binary
information.
Latch is an unclocked flip-flop.
Types:
SR
D
JK
T
S-R Latch with NORs
R (reset) Q S R Q Q
1 1 0 0 Undefined
1 0 1 0 Set
Q 0 1 0 1 Reset
S (set) 0 0 0 1 Stable
1 0

S-R latch made from cross-coupled NORs

If Q = 1, set state
If Q = 0, reset state
Usually S=0 and R=0
S=1 and R=1 generates unpredictable results
 SR Latch Analysis

Consider the four possible cases:

a) S = 1, R = 0
b) S = 0, R = 1
c) S = 0, R = 0
d) S = 1, R = 1
 SR Latch Analysis
0 11
a) S = 1, R = 0: then Q = 1 and Q = 0 R
N1 Q
00

10
0
0
1 N2 Q
S

b) S = 0, R = 1: then Q = 0 and Q = 1 1 00
R
N1 Q
1
1

0
0
11
0 N2 Q
S
 SR Latch Analysis
c) S = 0, R = 0: then Q = Qprev and Q = Qprev We got Memory!
Qprev = 0 Qprev = 1

0 00 0 11
R R
N1 Q N1 Q
11 00

00 11
11 00
0 N2 Q 0 N2 Q
S S

d) S = 1, R = 1:
then Q = 0 and Q = 0 Invalid state: Q NOT Q
1 00
R
N1 Q
00

00
00
1 N2 Q
S
 TRUTH TABLE
INPUTS Present Next state STATE
state
S R Qn Qn+1 Qn+1

0 0 0 0 1 NO
CHANGE
1 1 0
0 1 0 0 1
RESET
1 0 1
1 0 0 1 0
SET
1 1 0
1 1 0 0 0 INDETER
MINATE
1 0 0
 S-R Latch with NANDs(ACTIVE LOW):

S
Q
S R Q Q
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 0 1 Reset
Q
R 1 1 0 1 Store
1 0

Latch made from cross-coupled NANDs

Sometimes called S-R latch
Usually S=1 and R=1
S=0 and R=0 generates unpredictable results
A) S=0, R=1
SET

B) S=1, R=0
RESET
C) S=1, R=1 (NO CHANGE)

D) S=0, R=0 (PROHIBITED)

 inputs Present Next state
state
S R Qn Qn+1 Qn+1 STATE

0 0 0 1 1 INDETER
MINATE
1 1 1
0 1 0 1 0
SET
1 1 0
1 0 0 0 1
RESET
1 0 1
1 1 0 0 1 NO
CHANGE
1 1 0
S-R Latches
 S-R Latch with NANDs(ACTIVE HIGH):

S R S R Q Q STATE

0 0 1 1 Q Q NO
CHANGE
0 1 1 0 0 1 RESET

1 0 0 1 1 0 SET

1 1 0 0 1 1 INDETER
MINATE
S-R Latch with control input
B) S=0, R=1 (RESET)
C) S=1, R=0 (SET)
D) S=1, R=1 (PROHIBITED)
 Triggering in flipflops
Level triggering (in latches)
Positive level triggering
Negative level triggering
Flipflops:
Pulse triggering (+ve & -ve)
Edge triggering (+ve & -ve)

Hi-Lo edge Lo-Hi edge

 Abstract Representations

D Q D Q

CK CK

D-Latch D-Flip Flop

(Positive Level Triggered) (Rising Edge Triggered)

D Q
D Q

CK
CK

D-Latch D-Flip Flop

(Negative Level Triggered) (Falling Edge Triggered)
Clocked SR Flip-Flop
 TRUTH TABLE

CLOCK S R Qn Qn+1 STATE

(enable)
0 X X X Qn no
change
1 0 0 0 0 no
change
1 1 1
1 0 1 0 0
RESET
1 1 0
1 1 0 0 1
SET
1 1 1
1 1 1 0 x INDETER
MINATE
1 1 x
 SR Flip Flop Waveform Diagrams :
To draw waveforms for flip flops you need to begin with an initial condition at Q, mark the
area where the clock input is asserted and then draw the output response. Lets use an
initial condition of Q =0.
The initial condition Q =0 is
marked as a dot on the output
waveform diagram.
Set
The flip flop has a negative edge
triggered clock. The clock is
asserted when Clk makes a
Reset transition from 1 to 0. The
asserted zone is marked off in
yellow.

Analyze the waveform and draw

Clock
Q.

Until
On
Onthe
this
thisclock
negative
negative
changes
edge
edgefrom
S=R=0:
S=11and
to No
0R=0:
it Change
is NOT
SET asserted.
Mode.
Mode.
Thus
ThusQQsetsholds
to at
1. Thus
0.
NoNoanalysis
Qanalysis
holds
is at
required
is 0.
requireduntil
until
thenext
next
S Q negative edge.

>Clk

R Q
 CHARACTERISTIC TABLE

S R Qn+1

SR
S 0 0 Qn
00 01 11 10
Q( t ) 0 1 0
0 0 0 X 1
1 0 1
1 1 0 X 1 1 1 ?
R EXCITATION/APPLICATION TABLE

Characteristic Equation: Qn Qn+1 S R

Q+ = S + R Q 0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
 D-Latch

C D Q
0 x No change
1 0 0
1 1 1

Advantages over S-R Latch

Single input to store 1 or 0
Avoid spurious input of S=1 and R=1
 D Latch Timing Diagram

clock

clock enables input to be seen

output follows input in here
 Clocked D Flip-Flop

Stores a value on the positive edge of C

Input changes at other times have no effect on output
 Clocked D Flip-Flop

D
3
1 Q

CP Q
2
4
5
 TRUTH TABLE EXCITATION/APPLICATION
TABLE

CLOCK D Qn Qn+1 STATE

(enable) Qn Qn+1 D

0 0 0
0 X X Qn no
change
0 1 1
1 0 0
1 0 0 0
RESET 1 1 1
1 1 0
CHARACTERISTIC TABLE
1 1 0 1
SET
D Qn+1
1 1 1
0 0
D
Q 0 1
1 1
0 0 1

1 0 1

Q+ = D
Clocked J-K Flip Flop
 TRUTH TABLE

CLOCK J K Qn Qn+1 Qn+1 STATE

0 X X X Qn Qn no
change
1 0 0 0 0 1 no
change
1 1 1 0
1 0 1 0 0 1
RESET
1 1 0 1
1 1 0 0 1 0
SET
1 1 1 0
1 1 1 0 1 0 TOGGLE
STATE
1 1 0 1
 CHARACTERISTIC TABLE

J K Qn+1
0 0 Qn

JK J 0 1 0
00 01 11 10 1 0 1
Q
1 1 Qn
0 0 0 1 1
1 1 0 0 1 EXCITATION/APPLICATION TABLE

K
Qn Qn+1 J K
Q+ = D = JQ + KQ
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
 Clocked J-K Flip Flop

Two data inputs, J and K

J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table
 J-K Latch: Race Condition

Set Reset Toggle

100

J
K
Q
\Q

Toggle Correctness: Single State change per clocking event

Solution: Master/Slave Flipflop

 TRUTH TABLE

CLOCK J K Qn Qm Qs

0 0 0 0 NC

0 NC 0
1 1 NC

1 NC 1
0 1 0 0 NC

0 NC 0
1 0 NC

1 NC 0
CLOCK J K Qn Qm Qs

1 0 0 1 NC

0 NC 1
1 1 NC

1 NC 1
1 1 0 1 NC

0 NC 1
1 0 NC

1 NC 0
Timing diagram for master-slave JK FLIPFLOP
Timing diagram for master-slave JK LATCH
Timing diagram for a master-slave SR flip-flop
Timing diagram for a master-slave SR LATCH
Clocked T- Flip Flop
 Toggle Flip-Flops
J Q Q
T
K Q Q

clk

Q
 TRUTH TABLE

CLOCK T Qn Qn+1 Qn+1 STATE

0 X X Qn Qn no
change
1 0 0 0 1 no
1 1 1 0 change
1 1 0 1 0 TOGGL
1 1 0 1 E

CHARACTERISTIC TABLE
EXCITATION/APPLICATION TABLE

Qn Qn+1 T
T Qn+1
0 0 0
0 Qn
1 Qn 0 1 1
1 0 1
Q(t+1) = TQ(t) + TQ(t)
1 1 0
= T Q(t)
 Asynchronous Inputs
J, K are synchronous inputs
o Effects on the output are synchronized with the CLK input.
Asynchronous inputs operate independently of the synchronous
inputs and clock
o Set the FF to 1/0 states at any time.
Asynchronous Inputs
 Master-Slave Edge-Triggered Flip-Flop

Can connect two level-sensitive latches in Master-Slave

configuration to form edge-triggered flip-flop
Master latch catches value of D at QM when CLK is low
Slave latch causes Q to change only at rising edge of CLK
QM
D Q
Master Slave
Latch Latch
CLK 2 x 8 = 16 Transistors
CLK

CLK

QM

Q
 Alternative Edge-Triggered Flip-
Flop VDD VDD

Q CLK CLK

D Q
CLK
CLK CLK
Q

GND GND
D

24 Transistors 8 Transistors
 Flip-flop timings
1)Setup time: It is the minimum time for which the control levels
need to be maintained constant on the input terminals of the flip-
flop, prior to the arrival of the triggering edge of the clock pulse, in
order to enable the flip-flop to respond reliably.

2)Hold time: It is the minimum time for which the control levels
need to be maintained constant on the input terminals of the flip-
flop, after the arrival of the triggering edge of the clock pulse, in
order to enable the flip-flop to respond reliably.

3)Propagation Delay: It is the time interval between the time of

application of the triggering edge or asynchronous inputs and the
time at which the output actually makes a transition.

tPLH : It is measured from the triggering edge of clock pulse (or

preset input) to the LOW to HIGH transition of the output.
tPHL : It is measured from the triggering edge of clock pulse (or clear
input) to the HIGH to LOW transition of the output.
 Setup and Hold Times
Setup Time: How long a signal must be stable
D D Q Q preceding the clock edge

Hold Time: How long a signal must be stable after the

Clk clock edge

setup hold
time time

Clk

Setup: Pass Setup: Fail Setup: Pass Setup: Fail

Hold: Pass Hold: Pass Hold: Fail Hold: Fail
 Setup and Hold times: Flip Flops
20ns 5ns 20ns 5ns
74LS74 Positive
Edge Triggered
D Flipflop
Clk

23/13ns 40/25ns

Setup time 20ns

Hold time 5ns
Propagation delays
- Low to High 23 ns max, 13 ns typ
- High to Low 40 ns max, 25 ns typ
 Propagation Delays in an SR Latch

Propagation delay the time it takes a change in an

input signal to produce a change in an output
 CONVERSION OF FLIPFLOPS
1)SR FLIPFLOP TO D-FLIPFLOP:

INPUT(D) PRESENT NEXT FLIP FLOP INPUTS

STATE(Qn) STATE(Qn+1) S R
0 0 0 0 1
0 1 1 1 0
1 0 0 1 0
1 1 1 0 1

S=D

R=D
2)SR-FLIPFLOP TO JK-FLIPFLOP:
J K Qn Qn+1 S R
0 0 0 0 0 x
1 1 x 0
0 1 0 0 0 x
1 0 0 1
1 0 0 1 1 0
1 1 x 0
1 1 0 1 1 0
1 0 0 1

R Q Q
K
R = K + Qn
J S Q Q S = J + Qn
clk
3)D flipflop to JK Flip-Flop

J K Qn Qn+1 D
0 0 0 0 0
1 1 1
0 1 0 0 0
1 0 0
1 0 0 1 1
1 1 1
1 1 0 1 1
1 0 0

D = K Qn + J Qn
D flipflop to JK Flip-Flop

Q
D
K
Latch
Q
CLK
4)Toggle Flip-Flop from D-flipflop

Toggles stored value if T = 1 when CLK is

high
Q
T D
Latch
CLK

T Qn Qn+1 D
0 0 0 0
1 1 1 D = T Q(t)
1 0 1 1
1 0 0