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Cross-Talk Induced Noise and Influencing Factors
Cross-Talk Induced Noise and Influencing Factors
Measurement Capabilities
Demo
Simulation Capabilities
Q&A
Page 2
Signal Integrity requirements and Cross-talk
- over/under-shoot
- clock tCL/tCH
- clock monotonic
- Cross-Talk
- Clock Jitter
3
Data patterns and Cross-talk
Page 4
Data patterns and Cross-talk
Internally developed
Worst-Case
cross-talk pattern
Page 5
Flex Cables and Cross-talk
Cluster Type 1 RGB signals at display pins Cluster Type 1 RGB signals at display pins
With Shielded FFC With Unshielded FFC
Cluster Type 2 RGB signals at display pins Cluster Type 2 RGB signals at display pins
With Shielded FFC With Unshielded FFC
Page 6
Flex Cables and Cross-talk
Cluster Type 1 - RGB bus Pinout for display
R2
R0
R1
R3
R4
R5
Cluster Type 2 - RGB bus Pinout for display RGB data minimum voltage [mV]
R1 R3 R6 G1 G2 G3 B2 B5 B7
0
-50
-100
-150
-200
-250
-300
Page 7
Cross-talk in other modules display example
Evaluate crosstalk generated on RGB lines within the display 1, by injecting a square waveform
from signal generator directly into the display connector pin B2.
Johnson Controls
Page 8 8
Single PCB Cross-talk Simulation Capability
Manual Cross-talk evaluation using Hyperlynx 2 D
Page 9
Single PCB Cross-talk Simulation Capability
Perform simulations to minimize crosstalk between RGB traces
Page 10
Cross-talk on DDR3 data bus
DDR3 noise observed during Read operation
due to random
DQ0 - Measured crosstalk during DQ4 transitions
data read DQ0 Simulated crosstalk in Hyperlynx 2D due to DQ4 transitions
Page 11
Cross-talk on DDR3 data bus
Proper simulation of crosstalk on DQ0 line during Read required use of the TDR to
create an s-parameters model of coupling between DQ0 and DQ4
DQ0
DQ4
Page 12
Summary: Cross-talk sources and influencing factors
Page 13
Cross-talk sources and influencing factors
Q&A
Page 14