PDP Training

Agenda

1. Introduction to PDP

2. Manufacturing & Structure of Panel

3. PDP Driving Characteristics

4. Puccini Training

5. Trouble shooting
 1. Introduction to PDP
Concepts of PDP

Power supply
P/S UV radiation Phosphor
Visible Light
Driving circuit

R G B

Visible
emission

R G B

Generation Conversion
Transportation
 PDP?
Fluorescent Lamp and PDP
PDP .
2 0.1mm
Principle of PDP light emission is the same as fluorescent lamp.
, .
2 pieces of glass plates are placed with a small gap of 0.1mm, which is
100volt ,
filled with discharge gas, and one of the glass plate has a transparent
.
electrode. When 100 and several ten V of voltage is applied to the
R,G,B
electrodes, discharge starts and generates UV light. This UV light
.
reaches to the other glass plate on which phosphors (R,G,B) are pasted,
and the phosphors convert UV light to visible light.
PDP

< Fluorescent lamp > < PDP >

 History of PDP
3rd Generation

2nd Generation Size : 30-80 inch

Price : Under $10/inch
1st Generation Definition : CRT Grade
Size : 30-60 inch
Efficiency : 2-5 lm/w
Price : $10~$20/inch
FAN Noise : No Fan
Size : 20-50 inch Definition : CRT Grade
Preceding Use : Public
Price : $20~$30/inch Efficiency : 1-2 lm/w
Definition : PJTV FAN Noise
: Under 30db / No Fan New Production
Size : 20 inch Efficiency : 1-1.2 lm/w Technique
Price : $30~$50/inch FAN Noise : 35-45 db Use : High-Income bracket
Business
Efficiency : 0.5-1 lm/w Use : High-Income
bracket / Business Establishing Mass
Use : Business
Production Technique
Upgrading Mass
Upgrading Basic Production Technique
Technique

1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
 Merits & Demerits of PDP

< Merits > < Demerits >

- Thin Type TV - High Power Consumption
- Large Scale : 80 possible - Low Brightness
- Light Weight (42 Scale) - High Cost
: PDP 30kg / CRT: over 100kg - Low Lighting Efficiency
: LCD 40 32Kg - Image Retention
- Wide Angleview - Operation Temperature
- High Definition - Acoustic Noise of Driving
: cell pitch 0.1mm
- Not-Sensitive to Magnetic Field
- Full-color
- Good Non linerity
: No need for TFT like LCD
 Manufacturing &
Structure of Panel
 2. Manufacturing & Structure of Panel
Cell Structure of Panel

Bus electrode Front panel

Dielectric
MgO layer ITO electrode
Barrier Phosphors

Address Back panel

Electrode
 Cell Structure of Panel
 Electro Arrangement of PDP(SDI Panel - SD)

R1 G1 B1 R2 G2 B2 R3 R852 G852 B852

Y1
X

Y2

Black Stripe


Y480
X

Refer ence
- A 1,A 2, , , : A ddr es s E lectr ode
- Y 1,Y 2, , , : Scan & Sus tain E lectr ode
- X : Common & Sus tain E lectr ode
 Function of each PDP Cell Components

Gas Transparent Electrode

- Discharge - Forming Electric Field
- UV Generation - Transmitting visible Light

Dielectric Layer
- Current Limiting
- Transmitting visible Light
- Storing wall charge Bus Electrode
- Path of Discharge
MgO Thin Film Current
- 2nd Electron Radiation - Preventing
- Forming wall charge Voltage Drop

Phosphor Layer
- Conversion of Address Electrode Driving Circuit
UV Visible Light - RGB Data Signal Input - Discharge Switching
 Process of Panel Manufacturing
 Process of Panel Manufacturing
 PDP Driving
Characteristics
 3. PDP Driving Characteristics
Function Description by board - 1
.SMPS(Switching Mode Power Supply)
: It is the supplier to provide voltage and current to work the drive voltage and panel in each board.

.X-MAIN BOARD
: It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and
supplies X electrode of panel with the drive wave form via connector.

.Y-MAIN BOARD
: It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board
and provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board
in order.

.LOGIC MAIN BOARD

: It process image signal and performs buffering of the logic-main board (to create XY drive signal
and output) and the address driver output signal.
Then it supplies the output signal to the address driver IC(COF Module).
 Function Description by board - 2

.LOGIC BUFFER(E,F,G) : It delivers the data signal and control signal to the COF.

.Y-BUFFER (Upper,Lower)
: It is the board to impress the scan waveform on the Y board and consist of 2 boards
(upper board and lower board).
8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output).

.AC Noise Filter

: It has functions to remove noise(low frequency) coming from AC LINE and prevent surge.
It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.

.COF (Chip on Flexible)

: It impress the Va pulse to the address electrode in the address section and forms the
address discharge by electric potential difference with scanning pulse to be dismissed
by the Y electrode. It is made in the form of COF and one COF consists of 4 Data Drive IC
(STV7610A :96 Output), otherwise single scan is made of 7 COF.
 Effect of Wall Charge

X Y X Y

Vw1
Vex+Vw1 >Vf : Discharge
Vex
X Y X Y
X 0V
Vw2
Y 0V Vex-Vw2 < Vf : No discharge

X Y X Y

Vex < Vf : No discharge

Different Result with same input pulse Vex according to Wall Charge state
 1 Sub-Field Image Process(ADS Address Data Separate)

Reset Address Sustain

Function
Function Function
Sustain Erase
Select On Cell Discharge On Cell
Wall Charge Set
Issue Issue
Issue
High Speed High Efficiency
Operation margin
Low Voltage Low Voltage
Contrast
Low Failure ERC Performance
Short Time
 Driving Waveform Specification (P3 Alexander)
Reset Address Sustain

Y rising Y sustain
R am p P ulse

Y falling
R am p Y scan
P ulse
X sustain
P ulse

A ddress
P ulse

A1,2..... Address(=Data) Electrode Vs 85V Ve 110V

X Common & Sustain Electrode Vset 95V Va 79V
Y1,2.... Scan & Sustain Electrode Vscan 85V
 Address Operation

In order to display picture,

select the cells.
 Sustain Operation

Display cells through strong

Sustain discharge.
 Combination of R,G,B Light

1 - Pixel

Level of Luminance

RED 4096 Levels Green 4096 Levels Blue 4096 Levels

68.7 Billion Colors

 Luminance Control

Number
of Pulses 1 2 4 2048

Lights 1 2 4 2048
 1 Picture Structure by 12 Sub-Field - 1
 1 Picture Structure by 12 Sub-Field - 2
 1 Picture Structure by 12 Sub-Field - 3
 1 Picture Structure by 12 Sub-Field - 4
 1 Picture Structure by 12 Sub-Field - 5
 1 Picture Structure by 12 Sub-Field -
 1 Picture Structure by 12 Sub-Field - 11
 1 Picture Structure by 12 Sub-Field - 12
3. Puccini Training
 Comparison with other Models
Project Puccini(V4) Mozart (V3) Nelson (V3)
Design

Brightness 1300cd/m2 1000cd/m2 1000cd/m2

Contrast ratio 10000:1 3000:1 3000:1
Tuner 1Tuner 2Tuner 1Tuner
Audio out 15W x 2 15W x 2 15W x 2
Sound SRS Tru Surround XT SRS Tru Surround XT SRS Tru Surround XT
Speaker Included Included Not Included
Video input 1Rear 2Rear 1Rear
S-Video input 1Rear 1Rear 1Rear
Component 2Rear 2Rear 1Rear
Input
Side Input - CVBS, S-Video -
HDMI 1Rear - -
Power 290W 330W 330W
Consumption
Etc. - Touch Pad, Melody -
 Additional Function of PL42S5S
1. 12bits Signal process and 12bits Panel Drive
2. Energy saving Function

Function
MENU -> Picture -> Energy Saving

* Auto Saving (0 ~ 21% Power saving)

- Automatically adjusts to the surrounding illumination.
* Standard (No Power saving)
- Operates in standard mode regardless of
the surrounding illumination.
* Super Saving (21% Power saving)
- Enters maximum power saving mode regardless of
the surrounding illumination
 Picture of PL42S5S Set [Back view]
 Picture of Puccini PDP Module [Back view]
 PDP Set Block Diagram
[W hole B lo ck D iag ram ]
Y - M ain B 'd
X - M ain B 'd
Lo g ic B 'd D isp lay
D ata
Row P D P P anel
D river
D RAM D river 852 X 480 P ixels X - P ulse
Tim ing 853 X 3 X 480 C ells G enerato r
Inp ut D ata Y - P ulse
C o ntro ller D river
D ata G enerato r
Tim ing S can
P ro cesso r
C o ntro ller Tim ing
C o lum n D river
C lo ck :
C lo ck : C lo ck : 20M H z P o w er B 'd
27M H z 60M H z 40M H z

P o w er S up p ly

LV D S
m ain - B o ard

Im ag e D e- A ud io
E nhance interlacer P ro cesso r A C P o w er
r
Im ag e V id eo S o urce
V id eo
S calar D eco d er
Tuner 220 V
S /W
AD TM D S C om b
M ico m Filter
C o nverterr R eceiverr
 Wire Diagram
W ire D ia g ra m

DCDC
C N 4001
C N 5002 C N 5008 (9 P )
(1 2 P ) (1 0 P )
C N 5006 SM PS C N 4003
(1 7 P )
(1 3 P )
C N 5003
(1 2 P )
Y X C N 4004
(1 7 P )
C N 5004 C N 806
C N 802
(1 2 P )
C N 5007 C N 101 C N 4005
(1 3 P ) (3 0 P ) (1 7 P )
C N 5005 C N 5001 LA 0 3 C N 4002
(1 2 P ) (4 0 P ) (3 0 P )
C N 201 L O G IC

C N 401 C N 402 C N 403

(5 0 P ) (5 0 P ) (5 0 P )

C N 806 G -B U FF E R
E -B U FF E R F-B U F FE R

C N 1203
C N 1201

m ain
 Puccini (PS42S5S)
P S 4 2 S 5 S V id e o B lo ck D iag ram

JA 0 4 0 0 IC 4 0 0 8
TM DS D ig ital R ,G ,B
HDM I S il9 9 9 3
JA 0 4 0 1 A n alo g R ,G ,B
PC
IC 5 0 0
JA 0 8 0 3 A n alo g Y ,P b ,P r
D D R RA M
C o m p o n en t
JA 0 8 0 8 A n alo g C V B S
A V (V id e o ) IC 2 0 3
IC 5 0 2 IC 7 0 2
JA 0 8 0 7 A n alo g Y /C T E A 6425D
S cart m o n ito r o u t m ain C V B S ,Y /C ST P D ig ital R ,G ,B D N Ie
A V (S - V id e o )

JA 1 0 0 IC 2 0 2 S u b C V B S ,Y /C
S cart1 (C V B S ,Y /C ,R G B ) T E A 6425D IC 3 0 0
SA A 7119 D ig ital 6 5 6 D ig ital R ,G ,B
S cart R ,G ,B
JA 1 0 1 S cart C V B S ,Y /C
IC 2 0 0 IC 1 1 0 0
S cart2 (C V B S ,Y /C )
S cart C V B S ,Y /C T E A 6425D D T C 34L M 85A
S cart m o n ito r o u t IC 1 1 0 1
D T C 34L M 85A

A n te na
T U 1 _1 CV BS
In p u t
IC 6 0 1 SC L 1
SD A 1
M 30620SP G P SC L 0
SD A 0
JA 0 8 0 4 M o n ito r o u t C V B S
M o n ito r o u t IC 6 0 8 SC L 0
S3F 866B SD A 0
 P S 42S 5S S ound B lock D iagram
JA 0808 A V L /R
SC L 0/SD A
A V (S-V ideo/V ide
C om ponent L /R 0
o)
P C L /R
JA 0804 O ut_In1 L /R I2S
O ut L /R H D M I L /R IC 1000 O ut_In1 L /R
M onitor out IC 1004
T E A 642 O ut_In3 L /R O ut_In2 L /R
O ut_ L /R IC 1001 N SP 6241
2 O ut L /R
JA 0805 E xt1 L /R M SP 4410
H D M I L /R O ut_In3 L /R E xt1 L /R
HDM I G
E xt2 L /R
I2S
JA 0801
P C L /R
PC SC L 1/SD A 1
SC L 1/SD A 1
A V L /R O ut_ L /R
JA 0802 IC 1003
C om ponent L /R
C om ponent
Scart1 L /R IC 1002 O ut_In2 L /R T A S5112
T E A 642
Scart2 L /R 2
Scart1 L /R A nalog L /R
JA 100
Scart1 E xt1 L /R

Scart2 L /R SC L 1/SD A 1
JA 101
E xt1 L /R C N 1000
Scart2
C onnector
 Picture of PL42S5S main Board

 PL42S5S main IC Functional Description

No N am e Functio n

S TP m ain V id eo D eco rd er+ D einterlacer+ S caler

D N Ie Im ag e E nhancer

M 30620 S P G P m ain M ico m

S A A 7 119 sub V id eo D eco rd er

S IL9993 H D M I D eco rd er

S 3F 8668 sub M ico m

M S P 4410 G S o und p ro cesso r

N S P 624 1 S o und E ffe ct chip

TM Q H 6- 701A Tuner
 PL42S5S SW update method
1. Connect PC and PDP using RS-232C Cable

RS-232C Cable

2. Double click the Flash download program

 3. Click open button

4. Select Download source file(*.mot)

5. Connect Power cord and click Connect, click Program after being activated Program button

7. Flash Download Completed

6. Now SW upgrade is working

 Calibration (AV/Component/PC mode)
- Factory mode OSD
1. C alibratio n 7. YC D elay
2. O ptio n Table 8. A djust
3. W hite B alance 9. D N Ie
4. S VP -E X 10. C hip D ebugger O FF
5. S A A 7119 11. C hecksum
6. M S P 34X X /44X X 12. R eset
13. S pread S pectrum
T-P C N 42P E U S -X X X X 14. Lo gic
S U B M ico m Ver-x x x x

1. A V C alibratio n
2. P C C alibratio n
3. D TV C alibratio n

Lattice Pattern for Calibration (MSPG-925 LTH #24 Pattern)

* Calibration mode

1. AV mode : PAL
2. Component(DTV) mode : 1280X720@60Hz
3. PC mode :1024X768@60Hz

You must perform Calibration in the Lattice pattern before adjusting the White Balance
If you perform Calibration in a pattern other than the Lattice pattern, it causes a
malfunction and the operation will not finish
If you perform Calibration press the in remote control
 White Balance Adjustment
If picture color is wrong, check White Balance condition

Equipment : CA210, Patten : ABL Pattern

Adjust W/B in Factory Mode

Sub brightness and R/G/B Offset controls low light region

Sub contrast and R/G/B Gain controls high light region

Source AV : PAL composite, Component : 1280*720/60Hz

(PC and HDMI mode is adjusted automatically)

[ Test Pattern : MSPG-945 Series Pattern #16 ]

*Color coordinate
High Light
H/L : 265/265 +/- 2 30.0 Ft +/- 2.0Ft
L/L : 275/285 +/- 3 1.2 Ft +/- 0.2Ft

Low Light

Toshiba Patten
 Picture condition in Factory mode

No Item M ode R em ark

1 P icture m ode D ynam ic
2 C olor Tone m ode C ool1
3 P icture S ize Auto W ide C om ponent/P C /H D M I: W ide
4 D igitalNR O ff
5 D NIe D em o O ff
6 M CC C ustom
7 Energy S aving S tandard
8 P IP O ff
9 C olor W eakness O ff
- Factory mode OSD

1. C alibration 7. YC D elay
2. O ption Table 8. Adjust
3. W hite B alance 9. D NIe
4. S VP -EX 10. C hip D ebugger O FF
5. S AA7119 11. C hecksum
6. M S P 34XX/44XX 12. R eset
13. S pread S pectrum
T-P C N42P EU S -XXXX 14. Logic
S U B M icom Ver-xxxx
- Inside White Balance

No Item Range RF/AV Initial Com ponent Initial PC Initial HDM IInitial

1 Sub-Briteness 0~255 7 128 130 130

2 R-offset 0~255 138 128 138 138
3 G-offset 0~255 128 128 128 128
4 B-offset 0~255 146 128 144 144
5 Sub-Contrast 0~63 36 32 32 32
6 R-offset 0~255 128 128 128 128
7 G-offset 0~255 128 128 128 128
8 B-offset 0~255 148 128 128 128
4. Trouble shooting
 Check List in advance

. Each cable connection condition check

- Cable is connected correctly ?

.Check Voltage
- SMPS Video main Board, SMPS X,Y Drive board, SMPS Logic board

. The chart below shows abnormal condition

 No Power
- Not operate front LED

- Not operate SMPS relay

N
AC socket is connected
SMPS CN800 ?
Connect AC socket, SMPS CN800

N
Main SMPS Fuse(F801S) is open? Change Fuse(F801S)

Main SMPS CN804-1 N

#3 Pin : STB 5V ?
#5 Pin PS-ON : 0V ?
Change Main SMPS

Change main Board

 SMPS relay on <-> off continually

- Operate Protection circuit because of some Assy problem

Remove Main SMPS CN812, N Connect CN812, remove DC-DC
SMPS CN2,CN4,CN5 Relay
Relay ON <-> OFF after
Power on ? ON <-> OFF after Power on ?
N
Change DC-DC SMPS

Y
Y

Remove SMPS CN804-1,
CN803, Short CN804-1 N Remove only DC-DC SMPS CN4, N
#4Pin and #5 Pin Relay
ON <-> OFF after Powrer
on ?
Relay ON <-> OFF after
Power on ?
Change X Drive

Y
Y

Remove only DC-DC SMPS CN2, N
Change Main SMPS Relay ON <-> OFF after Change Y Drive
Power on ?

Y
Change main Board
Remove only DC-DC SMPS N
CN810, Relay ON <-> OFF Change Logic
after Power on ?
 No display but sound is normal
- X or Y or Logic or Y Buffer board is abnormal
- main SMPS or DC-DC SMPS output Voltage is abnormal
Remove Main SMPS CN812
N
Vs, Va Voltage is normal
after Power on ?
Change Main SMPS

Connect CN809, Remove

DC-DC SMPS CN2, CN4,

CN4, DC-DC SMPS output
Voltage is normal after N

Power on ? Change DC-DC SMPS

Y
Display is normal after changing Y Drive board ?

Display is normal after changing X Drive board ?

Display is normal after changing Logic Drive board ?

Display is normal after changing Y Buffer board ?

Change PDP Module

 No sound but display is normal
- Speaker wire is not connect
- Video main board sound part defect
- Speaker part defect
- Volume level is 0(Non-sense)

N
Connect speaker wire correctly? Connect or change speaker wire

main Board CN0900 Input

Voltage is normal ?
N
Change SMPS

Change Video main board

 PDP Dot Module SPEC SDI module

Item
A Zone B Zone Remark
Special Management Items
Product Type
1) It is Cell-Defect if there are dark, bright,
Dark 1 6
flickering cells over 2 points within
Bright 0 1
42"
(SD)
1.5cm in the boundary section.
Flickering 0 1

TOTAL 7

Dark 3 8
2) Before vibration/dropping test, it should
Bright 0 1 be decided whether the module is good
42"
(HD)
Flickering 1 2 / badness first.
TOTAL 10 And after vibration/dropping test,
Dark 3 8
if Cell-Defect happens more than
Bright 0 1
50"
preceding descriptions on Specification,
Flickering 1 2
it is Cell-Defect module.
TOTAL 10

Dark 3 8

Bright 0 1
63"
Flickering 1 2

TOTAL 10
 A-Zone / BZone Size

Zone B H/4

H Zone A H/2

H/4

W /4 W /2 W /4

F igure-5. M easuring A rea