Scribd Logo
Upload

Welcome to Scribd!

  • 32 views

    Introduction To VHDL: by BODDU Lokesh

    Uploaded by

    Kiran Gunasegaran
    VHDL is a hardware description language used to model digital circuits. It was initiated by the US Department of Defense in the 1980s. VHDL allows modeling at different levels of abstraction like behavioral, structural, and physical. Entities define component interfaces and architectures describe the internal logic. Concurrent statements model combinational logic while processes use sequential statements to model sequential logic. Test benches simulate designs by applying test vectors and monitoring outputs. Synthesis translates the RTL design into a gate-level netlist implementation.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Flag for inappropriate content

    You might also like

    Introduction To VHDL: by BODDU Lokesh

    Uploaded by

    Kiran Gunasegaran
    32 views22 pages
    VHDL is a hardware description language used to model digital circuits. It was initiated by the US Department of Defense in the 1980s. VHDL allows modeling at different levels of abstraction like behavioral, structural, and physical. Entities define component interfaces and architectures describe the internal logic. Concurrent statements model combinational logic while processes use sequential statements to model sequential logic. Test benches simulate designs by applying test vectors and monitoring outputs. Synthesis translates the RTL design into a gate-level netlist implementation.

    Original Description:

    Original Title

    Training

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PPT, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    VHDL is a hardware description language used to model digital circuits. It was initiated by the US Department of Defense in the 1980s. VHDL allows modeling at different levels of abstraction like behavioral, structural, and physical. Entities define component interfaces and architectures describe the internal logic. Concurrent statements model combinational logic while processes use sequential statements to model sequential logic. Test benches simulate designs by applying test vectors and monitoring outputs. Synthesis translates the RTL design into a gate-level netlist implementation.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as ppt, pdf, or txt
    32 views22 pages

    Introduction To VHDL: by BODDU Lokesh

    Uploaded by

    Kiran Gunasegaran
    VHDL is a hardware description language used to model digital circuits. It was initiated by the US Department of Defense in the 1980s. VHDL allows modeling at different levels of abstraction like behavioral, structural, and physical. Entities define component interfaces and architectures describe the internal logic. Concurrent statements model combinational logic while processes use sequential statements to model sequential logic. Test benches simulate designs by applying test vectors and monitoring outputs. Synthesis translates the RTL design into a gate-level netlist implementation.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as ppt, pdf, or txt
    of 22

    Introduction to VHDL

    By
    BODDU Lokesh
    VHDL Development
    • US DoD initiated in 80’s
    • Very High Speed ASIC Description
    Language
    Shortly About the VHDL
    • VHDL is an acronym of VHSIC Hardware
    Description Language
    • VHSIC is an acronym of Very High Speed
    Integrated Circuits

    • A Formal Language for Specifying the


    Behavior and Structure of a Digital Circuit
    • Allows Top-Down Design
    Levels of Abstraction
    • Digital system can be represented at
    different levels of abstraction
    – Behavioral—relationship between input and
    output signals, usually boolean expressions
    – Structural—description of the collection of
    gates and connections, more like a schematic
    – Physical
    Basic Design Methodology
    Requirements

    RTL Model Simulate

    Synthesize

    Gate-level
    Model Simulate Test Bench

    ASIC or FPGA Place & Route

    Timing
    Model Simulate
    Modularity
    • Every component in VHDL is referred to as an
    entity and has a clear interface
    • The interface is called an entity declaration
    • The “internals” of the component are referred
    to as the architecture declaration
    • There can be multiple architectures at even
    different levels of abstraction associated with
    the same entity
    Basic Structure of a VHDL File
    • Entity
    – Entity declaration:
    interface to outside
    world; defines input and
    output signals
    – Architecture: describes
    the entity, contains
    processes, components
    operating concurrently
    Modeling Interfaces
    • Entity declaration
    – describes the input/output ports of a module

    entity name port names port mode (direction)

    entity reg4 is
    port ( d0, d1, d2, d3, en, clk : in bit;
    q0, q1, q2, q3 : out bit ); punctuation
    end entity reg4;

    reserved words port type


    Architecture
    • Behavioral Model:
    architecture architecture_name of NAME_OF_ENTITY is
    -- Declarations
    …..
    …..

    begin
    -- Statements
    end architecture_name;
     
    VHDL Description: AND gate
    entity AND2 is
    a
    port (a, b: in bit ;
    AND c
    c : out bit);
    end AND2; b

    architecture beh of AND2 is


    begin
    c <= a and b;
    end beh;
    Processes
    • Used in behavioral modeling that allows you to use sequential statements to
    describe the behavior of a system over time
    [process_label:] process [ (sensitivity_list) ]
    begin
    list of sequential statements such as:
    signal assignments
    variable assignments
    case statement
    exit statement
    if statement
    loop statement
    next statement
    null statement
    procedure call
    wait statement
    end process [process_label];
    Full Adder – using Processes
    library ieee; -- Process P2 that defines the second half adder
    use ieee.std_logic_1164.all; and the OR -- gate
    entity FULL_ADDER is P2: process (int1, int2, Cin)
    port (A, B, Cin : in std_logic; begin
    Sum, Cout : out std_logic); Sum <= int1 xor Cin;
    int3 <= int1 and Cin;
    end FULL_ADDER; Cout <= int2 or int3;
      end process;
    architecture BEHAV_FA of FULL_ADDER end BEHAV_FA;
    is
    signal int1, int2, int3: std_logic;
    begin
    -- Process P1 that defines the first half adder
    P1: process (A, B)
    begin
    int1<= A xor B;
    int2<= A and B;
    end process;
    Structural Description
    • Carries same information as a NET LIST
    • Net List = (Component instances) + (Nets)
    • Structural Description in VHDL =
    (Signals) + (Component instances + Port maps)
    • Many sophisticated features in VHDL to make it
    more versatile:
    * Variety of signal types
    * Generic components
    * Generate statements for creating arrays of component instances
    * Flexibility in binding components to design entities and architectures
    Behavioral Description
    • Procedural • Non-procedural
    (textual order => execution (textual order NOT =>
    order) execution order)
    • Sequential statements • Concurrent statements
    • Data flow (or rather data
    • Control constructs alter dependency restricts
    normal sequential flow concurrency)

    Called Behavioral Called Data flow


    description in VHDL description in VHDL
    Example: D Flip-Flop
    entity DFF is
    port (D, CLK: in bit;
    Q: out bit; QN: out bit := ‘1’) ;
    end DFF;
    D Q
    DFF
    CLK QN
    Example: DFF (contd.)
    Architecture Beh of DFF is
    begin process (CLK)
    begin if (CLK = ‘1’ then
    Q <= D after 10 ns;
    QN <= not D after 10 ns;
    endif;
    endprocess;
    end Beh;
    Concurrent Conditional
    Assignment: 4 to 1 Multiplexer
    y <= x0 when sel = 0
    else x1 when sel = 1
    else x2 when sel = 2
    else x3 when sel = 3
    x0
    x1 y
    x2
    x3
    sel
    CASE Statement:
    4 to 1 Multiplexer
    Case sel is
    when 0 => y <= x0 x0
    when 1 => y <= x1 x1 y
    x2
    when 2 => y <= x2 x3

    when 3 => y <= x3


    end case
    Variables And Signals
    Architecture sig of dummy is
    signal trigger, sum: integer := 0;
    signal sig1: integer:= 1;
    signal sig3, sig2: integer:= 2;
    begin process
    begin wait on trigger;
    sig3 <= sig1 + sig2;
    sig1 <= sig3;
    sum <= sig1;
    end process; end sig;
    VHDL for Simulation & Synthesis

    Test Vector Executable Results,


    Specification
    = Errors
    Generator

    A Series of
    Test
    Refined
    Vectors
    Models
    Final Chip
    Model
    Test Benches
    • Testing a design by simulation
    • Use a test bench model
    – an architecture body that includes an instance
    of the design under test
    – applies sequences of test values to inputs
    – monitors values on output signals
    • either using simulator
    • or with a process that verifies correct operation
    Synthesis
    • Translates register-transfer-level (RTL)
    design into gate-level netlist
    • Restrictions on coding style for RTL model
    • Tool dependent
    – see lab notes

    You might also like