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Library, Components and Configurations: Dr. Yann-Hang Lee Yhlee@asu - Edu
Library, Components and Configurations: Dr. Yann-Hang Lee Yhlee@asu - Edu
Configurations
Dr. Yann-Hang Lee
yhlee@asu.edu
Design Hierarchy
library_name.package_name.ALL
even if the library_name is WORK
package_name.object -
requires that the package be defined in the same file
library_name.package_name.object
Examples:
library ASIC;
use ASIC.gate_array.all;
library IEEE;
use IEEE.std_logic_1164.all;
types, operators, and functions for detailed modeling
of logical data (of multivalued logic type)
std_ulogic, std_logic, type conversion, overloaded operator
use IEEE.std_logic_arith.all;
a set of arithemtic, conversion, and comparison
functions
for SIGNED, UNSIGNED, SMALL_INT, INTEGER,
STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR.
entity Test is
port (S1, S2 : in bit; Q : out bit);
end Test;
architecture Structure of Test is
signal A, B, S : bit_vector(0 to 3);
component Nor2
port (I1, I2: in bit; O: out bit);
end component;
begin
Q1: Nor2 port map (I1 => S1, I2 => S2, O => Q);
Add: for i in 0 to 3 generate
Comp: Nor2 port map (I1 => A(i), I2 => B(i), O=> S(i));
end generate;
end Structure;
entity computer_system is
end entity computer_system;
architecture structure of computer_system is
component decoder_2_to_4 is
generic ( p_delay : delay_length );
port ( in0, in1 : in bit; out0, out1, out2, out3 : out bit );
end component decoder_2_to_4;
begin
interface_decoder : component decoder_2_to_4
generic map ( p_delay => 4 ns )
port map ( in0 => addr(4), in1 => addr(5),
out0 => interface_a, out1 => interface_b,
out2 => interface_c, out3 => interface_d);
-- . . .
end architecture structure;
CSE 422 page 20
Example (continued)
entity decoder_3_to_8 is
generic ( Tp_01, Tp_10 : delay_length );
port ( s0, s1, s2 : in bit; enable : in bit;
y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
end entity decoder_3_to_8;
for structure
for interface_decoder : decoder_2_to_4
use entity work.decoder_3_to_8(basic)
generic map ( Tp_01 => p_delay, Tp_10 => p_delay )
port map ( s0 => in0, s1 => in1, s2 => '0', enable => '1',
y0 => out0, y1 => out1, y2 => out2, y3 => out3,
y4 => open, y5 => open, y6 => open, y7 => open );
end for;
end for;
end configuration computer_structure;
component inverter
port (a : in bit; y : out bit);
end component;
end package misc;
--
CSE 422 page 24
Entity Declaration - count2