SLEEP TRANSISTOR

DESIGN
Sleep Transistor is High Vt transistor
Used as a switch to off shut the power supply
to the parts of a design in standby mode
PMOS controls VDD supply
PMOS is called as Header switch
NMOS controls VSS supply
NMOS is called as Footer switch
 Design Metrics
Switch Efficiency

Area Efficiency

IR Drop
 Switching efficiency
• Switching efficiency is defined as the ratio of
the current in ON and OFF states ie Ion/Ioff
• High drive current in normal mode and low
leakage in sleep mode are essencial
• The efficiency varies with gate length , width
and body bias
• Optimal values of L,W and Vdd varies with
technology and process
SPICE analysis circuit to measure
on and off currents
Switching efficiency
Switching efficiency
 Area efficiency
• Area efficiency is defined by the ratio of its
drive current and silicon area i.e. Ion/Asleep
• Ion is the driving current when transistor is ON
and biased at Vds equating IR drop target.
• Asleep is the silicon area of the transistor
depending on L, W and layout implementation
• It is normally designed by connecting a
number of small transistors in parallel in
multi-finger style
 IR drop
• IR drop on sleep transistor depends upon
equivaqlent channel resistance Ron=Vds/Ion
when sleep transistor is conducting

• The smaller Ron , the smaller is IR drop

Gate length vs channel resistance
Body bias vs Threshold voltage
Body bias vs Leakage current
Transient simulation for inrush and
latency analysis