Ch.8 Flip-Flops and Related Devices

Ch.
8 Flip-Flops and
Related Devices
 Latch
 Edge-Triggered and Master-Slave Flip-Flops
 Flip-Flop Operating Characteristics
 Flip-Flop Applications
 One-Shots and the 555 Timer
 Troubleshooting
 Programmable Logic: Registered Operation
 Latches and Flip-Flops Using VHDL
Introduction 2
Digital Logic
(1) Combinational Logic Circuit, (2) Sequential Logic Circuit
Combinational Logic Circuit
Y=f(X) X: the finite set of input symbols

X
f Y: the finite set of output symbols
n m
f: a Boolean function for the output
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3
Sequential Logic Circuit
Latches, Flip-flops
RAM, etc.

Finite State Machine 4
X f Y=f(X,S)
n m
g
K
S
Storage Device Status S+=g(X,S)
X : the finite set of input symbols

Y : the finite set of output symbols
S : the finite set of status symbols, S  2K
f : a Boolean functions(logic diagram) for output Y
g : a Boolean functions for next state S+

5

Multivibrators 6
1. Bistable Multivibrator: latches and flip-flops

 Has two stable states
2.Monostable Multivibrator: one-shot
 Has one stable state
3.Astable Multivibrator: clock
 Has no stable state
Q : ‘1’ or ‘0’ Q
Latch / One-
flip-flop Q’ shot Q’ Clock

Latches 7
• The S-R (Set-Reset) Latch

– A type of bistable multivibrator
– Store one bit
( 걸쇄 , 빗장 )
Figure 8-1 Two versions of SET-RESET (S-R) latches. Open file

F08-01 and verify the operation of both latches.

QQ’=1 8
Normally HIGH input

9
Input Output
Comments
S’ R’ Q Q’
0 0 1 1 Not allowed
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q Q’ No change

10
Figure A-13 The 74xx279 quad S’-R’ latch.

Application Example : Latches 11
• The Latch as a Contact-Bounce Eliminator
S’: 1 1 1 1 • • • 1 0 1 0 0 • • •
No change R’: 0 1 0 1 • • • 1 1 1 1 1 • • •

The Gated S-R Latch 12
• Requires an enable input(EN) (G is also used to

designate an enable input)
Figure 8-7 A gated S-R latch.

13

The Gated D Latch 14

15
Figure A-14 The 74xx75 quad gated D latches.

Edge-Triggered Flip-Flops 16
• Edge-triggered flip-flop changes state either at the positive

edge(or rising edge) or at the negative edge(falling edge) of
clock pulse and is sensitive to its inputs only at this transition of
clock
+ T-flip-flop
Figure 8-11 Edge-triggered flip-flop logic symbols (top: positive edge-

triggered; bottom: negative edge-triggered).

The Edge-Triggered S-R Flip-flop 17

18
Input Output
Comments
S R Q Q’
0 0 Q Q’ No change
0 1 1 0 Set
1 0 0 1 Reset
1 1 ? ? Not allowed

19
• A method of Edge-Triggering

20

The Edge-Triggered D Flip-flop 21
Input Output
Comments
D Clk Q Q’
0  0 1 Reset
1  1 0 Set
Figure 8-18 A positive edge-triggered D flip-flop formed with

an S-R flip-flop and an inverter/ truth table

The Edge-Triggered J-K Flip-flop 22
Figure 8-20 A simplified logic diagram for a positive edge-triggered J-K flip-flop.
toggle
Figure 8-21 Transitions illustrating the toggle operation when J=1 and K=1.

23
Input Output
Comments
J K Clk Q Q’
0 0  Q Q’ No change
0 1  0 1 Reset
1 0  1 0 Set
1 1  Q’ Q Toggle
Ex 8-7)

State Equation of J-K Flip-flop 24
Input Output
Comments JK
J K Q(t) Q(t+1)
Q(t) 00 01 11 10
0 0 0 0 No change
0 1 1
0 0 1 1 No change
11 1
0 1 0 0 Reset
0 1 1 0 Reset
1 0 0 1 Set
1 0 1 1 Set State Equation

1 1 0 1 Toggle Q(t+1) = JQ(t)’ + K’Q(t)
1 1 1 0 Toggle

25
Ex 8-6)

The Edge-Triggered T Flip-flop 26
Input Output Clk

Comments
T Clk Q Q’
T
0  Q Q’ No change
1  Q’ Q Toggle Q

Asynchronous Preset and Clear Inputs 27
• An active preset input makes the Q output

high(set)
• An active clear input makes the Q output low(reset)
Figure 8-24 Logic

symbol for a J-K
flip-flop with active-
LOW preset and
clear inputs.

28
Ex 8-8)

29
Ex 8-9) For a negative edge-triggered flip-flop,

determine the Q output waveform
toggle

30
Figure A-14 The 74xx75 quad gated D latches.

Figure A-15 Logic symbols for the 74xx74 dual positive
edge-triggered D flip-flops. 31

Figure A-16 Logic symbols for the 74xx112 dual negative
edge-triggered J-K flip-flops. 32

Master-Slave Flip-Flops 33
• The pulse-Triggered Master-Slave J-K Flip-flop
master slave
Figure 8-28 Basic logic diagram for a master-slave J-K flip-flop.

34
Input Output
Comments
J K Clk Q Q’
0 0 Q Q’ No change
0 1  0 1 Reset
1 0  1 0 Set
1 1  Q’ Q Toggle
Ex 8-9) For a active LOW

clock master-slave J-K
flip-flop, determine the Q
output waveform

Flip-Flop Operating Characteristics 35
• Propagation Delay times

1. tPLH as measured from the triggering edge of
clock pulse to the LOW-to-HIGH transition of
the output
2.tPHL as measured from the triggering edge of
clock pulse to the HIGH-to-LOW transition of
the output
Figure 8--31 Propagation delays, clock to output.

36
3. tPLH as measured from the triggering edge of the

preset input to the LOW-to-HIGH transition of
the output
4. tPHL as measured from the triggering edge of the
clear input to the HIGH-to-LOW transition of
the output
Figure 8-32 Propagation delays, preset input to output and clear input to output.

Set-up Time/ Hold Time 37
Figure 8--33 Set-

up time (ts). The logic
level must be present
on the D input for a
time equal to or
greater than ts before
the triggering edge of
the clock pulse for
reliable data entry.
Figure 8-34 Hold time
(th). The logic level
must remain on the D
input for a time equal
to or greater than th
after the triggering
edge of the clock pulse
for reliable data entry.

Maximum Clock Frequency 38
• The maximum clock frequency(fMAX): the highest rate

at which a flip-flop can be reliably triggered
– is determined by propagation delay times, se-up, and hold
times
• Pulse Widths(tW)
– is determined by se-up, and hold times
• Power Dissipation
P = VCC X ICC
Ex) power requirement: 5V X 5mA = 25mW/flip-flop

10 flip-flops require 25 X 10 =250 (mW) and 50 mA

Comparison of operating parameters for four IC families of
flip=flops of the same type at 25°C 39
CMOS TTL
Parameter
74HC74A 74AHC74 74LS74A 74F74
tPHL(Clk to Q) 17 ns 4.6 ns 40 ns 6.8 ns
tPLH(Clk to Q) 17 ns 4.6 ns 25 ns 8.0 ns
tPHL(Clr’ to Q) 18 ns 4.8 ns 40 ns 9.0 ns
tPLH(Pre’ to Q) 18 ns 4.8 ns 25 ns 6.1 ns
ts(set-up time) 14 ns 5.0 ns 20 ns 2.0 ns
th(hold time) 3.0 ns 0.5 ns 5 ns 1.0 ns
tW(Clk HIGH) 10 ns 5.0 ns 25 ns 4.0 ns
tW(Clk LOW) 10 ns 5.0 ns 25 ns 5.0 ns
tW(Clr’/Pre’) 10 ns 5.0 ns 25 ns 4.0 ns
fmax 35 MHz 170 MHz 25 MHz 100 MHz
Power, quiescent 0.012 mW 1.1 mW
Power, 50% duty 44 mW 88 mW

Flip-Flop Applications 40
Application Examples
1. Parallel Data Storage(register stores a word)
0
1
1
0
Figure 8-35 Example of
flip-flops used in a basic
register for parallel
data storage.

41
2. Frequency Division( 주파수 분주 )
Figure 8-37 Example of two

Figure 8-36 The J-K flip- J-K flip-flops used to divide
flop as a divide-by-2 device. the clock frequency by 4. QA
Q is one-half the frequency is one-half and QB is one-
of CLK. fourth the frequency of CLK.

42
Ex 8-11) Develop the fout waveform when fin is 8 kHz.
fin/2
fin/8
fin/4
Sol)
8KHz
4KHz
2KHz
1KHz

43
3. Counting(asynchronous: same as frequency

division)
Figure 8-40 Flip-flops

used to generate a binary
count sequence. Two
repetitions (00, 01, 10, 11)
are shown.

44
Ex 8-12) Determine the output waveforms for each

output of flip-flops
Sol)

One-Shots(monostable multivibrator) 45
• A one-shot produces a single pulse each time it is

triggered.
td RC(time constant)
Figure 8-44 Basic one-

shot logic symbols. CX
Figure 8-43 A simple one-shot circuit. and RX stand for
external components.

46
Figure 8-45 Nonretriggerable one-shot action.
Figure 8-46 Retriggerable one-shot action.

47
Application Example
Figure 8-47 A sequential timing circuit using three one-shots.

48
Figure A-17 Logic symbols for the 74121 nonretriggerable

one-shot.

49
Figure A-18 Three ways to set the pulse width of a 74121.

50
Figure A-20 Logic symbol for the 74xx122 retriggerable

one-shot.

The 555 Timer(astable multivibrator) 51
Monostable(one-shot) Operation
tW=1.1R1C1
Figure 8-48 Internal

functional diagram of a 555
timer (pin numbers are in
parenthesis). Figure 8-49 The 555 timer
connected as a one-shot.

52
Figure 8-50 One-shot

operation of the 555 timer.

Astable Operation 53
Figure 8-51 The 555 timer Figure 8-52 Operation of the

connected as an astable 555 timer in the astable mode.
multivibrator (oscillator).

54
f= 1.44/((R1+2R2)C1)
R2>R1, tH = 0.7(R2 + R1)C1 , tL = 0.7R2C1
T = tH + tL = 0.7(R1 + 2R2)C1
Duty cycle = tH/T = tH/(tH+tL) = (R1+R2)/(R1+2R2)100%
tH tH
tL tLt tL
L
Figure 8-53 Frequency of
oscillation as a function of C1
and R1 + 2R2. The sloped lines
are values of R1 + 2R2.

55
Ex 8-14) Determine the frequency and duty cycle
Sol) f= 1.44/((R1+2R2)C1)
= 1.44/((2.2k+2x4.7k)0.022F)
= 5.64 kHz
Duty cycle= (R1+R2)/(R1+2R2)100%
=(2.2k + 4.7k)/(2.2k +2X4.7k)100% = 59.5%

Troubleshooting 56
• Glitch problem in two-phase clock generator
Figure 8-56 Two-phase clock generator with ideal waveforms.

57
Figure 8-57 Logic analyzer displays for the circuit in Figure

8-56.

58
Figure 8-58 Two-phase clock generator using negative edge-
triggered flip-flop to eliminate glitches.

Programmable Logic: Registered Operation59
• The Registered Logic in a Programmable Logic

Device
Figure 8-59 Generic CPLD/FPGA registered logic.

60
Figure 8-60 Combinational(a) and registered(b) output configurations.

Latches and flip-flops using VHDL 61
• The S-R latch can be either high or low inputs

• Q and QNOT are both inputs and outputs, VHDL
has a bi-directional mode inout which is used in
the port statement
port( S, R: in std_logic; Q, Qnot: inout std_logic);

S-R latch in VHDL 62
library ieee;
use ieee.std_logic-1164.all;
entity SRlatch is
port( S, R: in std_logic; Q, Qnot: inout
std_logic);
end entity Srlatch;
architecture Latch_Operation of SRlatch is
begin
process(S,R) is
begin
Q <= Qnot nor S;
Qnot <= Q nor R;
end process;
end architecture Latch_Operation;
S-R latch to S-R Flip-flop 63
• The S-R flip-flop may use a clock pulse

• The clock pulse needs to be an edge trigger event
• Using the VHDL statement wait until
rising_edge(clock) will cause the program to be
driven by the clock

VHDL for Rising edge-triggered, active high input S-R Flip-flop 64
library ieee;
entity SRFlipFlop is
port(S, R, Clock: in std_logic; Q, QNot: inout std_logic);
end entity SRFlipFlop;
architecture FlipFlopBehavior of SRFlipFlop is
begin
process(S,R,Clock) is
begin
wait until rising_edge(Clock);
if S=‘1’ and R=‘0’ then Q<=‘1’;
elsif S=‘0’ and R=‘1’ then Q<=‘0’;
else Q<=Q;
end if
QNot<= not Q;
end process;
end architecture FlipFlopBehavior;

65
Figure 8-64 S-R flip-flop simulation waveform.

VHDL for Rising edge-triggered, active high input D Flip-flop 66
library ieee;
entity DFlipFlop is
port(D, Clock: in std_logic; Q, QNot: inout std_logic);
end entity SRFlipFlop;
architecture FlipFlopBehavior of DFlipFlop is

begin
process(D, Clock) is
begin
if D=‘1’ then Q<=‘1’;
else Q<=Q;
end if
QNot<= not Q;
end process;
end architecture FlipFlopBehavior;

Re-usable packages(Programs) 67
• Make S-R latch a package and use it many times

• Using a VHDL package allows the use of the S-R
latch in the construction of other logic devices
– Refer the VHDL code on the next page(p.68)
Ex 8-18) Write the VHDL code to implement an
active-LOW input J’-K’ flip-flop with positive edge-
triggering using the previously defined package,
SRPackage.
J’ Q
F/F
K’ Q’

68
library ieee;
package SRPackage is
procedure ActiveLowSRlatch(SNot, RNot: in std_logic;
Q, QNot: inout std_logic);
end SRPackage;
package body SRPackage is
procedure ActiveLowSRlatch(SNot, RNot: in std_logic;
Q, QNot: inout std_logic) is
begin
if SNot=‘1’ and RNot=‘0’ then Q:=‘0’; QNot:=‘1’;
elsif SNot=‘0’ and RNot=‘1’ then Q:=‘1’; QNot:=‘0’;
elsif SNot=‘0’ and RNot=‘0’ then Q:=QNot; QNot:= not Q;
end if -- not included “11: no changed” condition
end ActiveLowSRlatch;
Toggle replaces
end SRPackage; invalid S’-R’ condition

Sol) the VHDL code for active-LOW input J’-K’ flip-flop with 69
positive edge-triggering using the previously defined package,
SRPackage in Ex 8-18.
library ieee;
use work.SRPackage.all;
entity ActiveLowJK is
port(JNot, Knot, Clock: in std_logic; X, Y: inout std_logic);
end entity ActiveLowJK;
architecture JKBehavior of ActiveLowJK is J’ S’ Q X
V1
begin F/F
process(JNot, KNot)
variable V1, V2: std_logic; K’ R’ Q’ Y
begin V2
FF1: ActiveLowSRlatch(SNot=>JNot, RNot=>Knot, Q=>V1, QNot=>V2);
X<= V1;
Y<= V2;
end process; Procedure
end JKBehavior; call

70
Figure 8-67 J’-K’ flip-flop simulated waveforms. Outputs X and

Y are initialized to valid states after the first clock pulse.

J-K Flip-Flop Components 71
• In example 8-18, a modified S-R latch package was

used to define the J-K flip-flop
• The J-K flip-flop will be made into a component
for used in a frequency divider
component JKFlipFlop is
port( J,K,Clock: in std_logic; Q: inout std_logic);
end component JKFlipFlop;
VHDL keyword buffer

• Similar to in out and inout used in a port statement
• buffer is unidirectional
port(clock: in std_logic; Qa, Qb, Fout: buffer std_logic);

72
Ex 8-19) Write a VHDL description of the frequency

divider in figure below using previously defined
component JKFlipFlop and develop the fout waveform
buffer

73
Sol) library ieee;

entity FreqDivider is
port(clock: in std_logic; Qa, Qb, fout: buffer std_logic);
end entity FreqDivider;
architecture FreqDivBehavior of FreqDivider is
port(J, K, Clock: in std_logic; Q: inout std_logic);
signal I: std_logic A unique user defined
label is assigned to each
begin component installation
I<=‘1’;
FFA: JKFlipFlop port map(J=>I, K=>I, Clock=>clock, Q=>Qa);
FFB: JKFlipFlop port map(J=>I, K=>I, Clock=>Qa, Q=>Qb);
FFC: JKFlipFlop port map(J=>I, K=>I, Clock=>Qb, Q=> fout);
end architecture FreqDivBehavior;

Relation of VHDL software to HW Implementation 74
• Use working code to make more complex code

• Complex operations can often be better described
using the behavioral approach
• The VHDL complier will decide how to implement
the code
• This allows the code to be usable on other
programmable devices
VHDL Approach Model and its Abstraction

1. Structural model
2.Dataflow model
3.Behavioral model Abstraction level : HIGH

Digital System Application 75
Traffic Light Controller System

• Requirements for the Timing Circuits

76
• Frequency divider(divide by 210)

– 25.175/(210)MHz = 25175/1024 KHz=24.585 KHz

‘1’ fout
77
J Q Qa J Q Qb Qi J Q
Clock Clock •••• Clock
K QNot K QNot K QNot
library ieee;
entity FrequencyDivider is
port(clock: in std_logic; fout: buffer std_logic);
end entity FrequencyDivider;
architecture FreqDivBehavior of FrequencyDivider is
signal Qa, Qb, • • • , Qi, I : std_logic;
port(J, K, Clock: in std_logic; Q, QNot: inout std_logic);
begin
I<=‘1’;
FF1: JKFlipFlop port map(J=>I, K=>I, Clock=>clock, Q=>Qa);
FF2: JKFlipFlop port map(J=>I, K=>I, Clock=>Qa, Q=>Qb);
•••••••••
FF10: JKFlipFlop port map(J=>I, K=>I, Clock=>Qi, Q=> fout);
end architecture FreqDivBehavior;

VHDL Code for Variable Count Timer 78
library ieee;
entity Timer is
port(Enable, Clock: in std_logic; SetCount: in integer; Qout : buffer
std_logic);
end entity Timer;
architecture TimerCounter of Timer is
begin
process(Enable, Clock)
variable Cnt: integer;
begin
if(Clock’Event and Clock=‘1’) then
if Enable=‘0’ then
Cnt:=0; Qout<=‘1’;
elsif Cnt=SetCount-1 then Enable
Qout<=‘0’; SetCount Qout
else Clock
Cnt:=Cnt+1;
end if;
end if;
end process;
end architecture TimerCounter;

State Equations for Flip-Flops(***) 79
• The logic equations for the next state of

the flip-flop
Q(t+1) = f(X, Q(t)), where X is the flip-flop input
and Q(t) is the current state of the flip-flop
D flip-flop T flip-flops
Input Output Q(t+1) = D Input Output Q(t+1) = T’Q(t)
D Q(t) Q(t+1) T Q(t) Q(t+1) +TQ(t)’ = TQ(t)
0 0 0 0 0 0
0 1 0 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

J-K Flip-flop 80
Input Output
Comments JK
J K Q(t) Q(t+1)
Q(t) 00 01 11 10
0 0 0 0 No change
0 1 1
0 0 1 1 No change
11 1
0 1 0 0 Reset
0 1 1 0 Reset
1 0 0 1 Set
State Equation(J-K flip-flop)
1 0 1 1 Set
Q(t+1) = JQ(t)’ + K’Q(t)
1 1 0 1 Toggle
1 1 1 0 Toggle
How is it for S-R flip-flop?

Excitation(or Transition) Tables for Flip-Flops(***)81
• The input conditions for the state

transitions of each flip-flop
Excitation Tables for D, T, J-K, and S-R flip-flops
State F/F State F/F State F/F State F/F
Change input Change input Change input Change input
Qt Qt+1 D Qt Qt+1 T Qt Qt+1 J K Qt Qt+1 S R
0 0 0 0 0 0 0 0 0 X 0 0 0 X
0 1 1 0 1 1 0 1 1 X 0 1 1 0
1 0 0 1 0 1 1 0 X 1 1 0 0 1
1 1 1 1 1 0 1 1 X 0 1 1 X 0
SR=1 : not allowed
Ex) State: 00 J K: 0 0
01
0X
Summary 82
• Symbols for latches and flip-flops
+ T type

Summary ( 계속 ) 83
• Multivibrators
– Bistable(latches and flip-flops): two stable states
– Monostable Multivibrator(one-shot or single-shot): one
stable state, time  Ext R and Ext C
– Astable Multivibrator(clock or oscillator): no stable state,
time  Ext R and Ext C
• Latches: normally depends on asynchronous inputs
• Edge-triggered flip-flops
• Pulse-triggered master-slave flip-flops
• Asynchronous inputs for preset or clear the flip-
flops
• VHDL
– inout(a bidirectional port), wait until rising_edge(clock),
wait until falling_edge(clock), buffer(a port read and
updated)
• State equations and Excitation tables for flip-
flops(*)
End of Chapter 8

Ch.8 Flip-Flops and Related Devices

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Ch.

Combinational Logic Circuit

Y=f(X) X: the finite set of input symbols

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Sequential Logic Circuit

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X : the finite set of input symbols

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1. Bistable Multivibrator: latches and flip-flops

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• The S-R (Set-Reset) Latch

Figure 8-1 Two versions of SET-RESET (S-R) latches. Open file

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Normally HIGH input

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Figure A-13 The 74xx279 quad S’-R’ latch.

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• The Latch as a Contact-Bounce Eliminator

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• Requires an enable input(EN) (G is also used to

Figure 8-7 A gated S-R latch.

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Figure A-14 The 74xx75 quad gated D latches.

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• Edge-triggered flip-flop changes state either at the positive

Figure 8-11 Edge-triggered flip-flop logic symbols (top: positive edge-

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Figure 8-18 A positive edge-triggered D flip-flop formed with

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1 0 1 1 Set State Equation

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Input Output Clk

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• An active preset input makes the Q output

Figure 8-24 Logic

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Ex 8-9) For a negative edge-triggered flip-flop,

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Figure A-14 The 74xx75 quad gated D latches.

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• The pulse-Triggered Master-Slave J-K Flip-flop

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Ex 8-9) For a active LOW

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• Propagation Delay times

Figure 8--31 Propagation delays, clock to output.

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3. tPLH as measured from the triggering edge of the

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