Professional Documents
Culture Documents
300 Alrudainy 48 Slides Modify1
300 Alrudainy 48 Slides Modify1
Mechanical Relays
Haider M. Alrudainy ,
1 Dr. Andrey Mokhov ,
2 Prof. Alex Yakovlev 3
School of Electrical and Electronic Engineering, Newcastle University, Newcastle Upon Tyne, GB
1h.m.a.alrudainy@ncl.ac.uk,2andrey.mokhov@ncl.ac.uk,3alex.yakovlev@ncl.ac.uk
(Ccg +Ccb ) ≪ Cgb , (Ccg +Ccb ) ≪ Cgd , (Ccg +Ccb ) ≪ Cgs (Ccg +Ccb ) could be ignored. g
Needed Switch simulator: 𝑅𝑡𝑟𝑎𝑐𝑒 ≪ 𝑅𝑝𝑜𝑥 , 𝑅𝑡𝑟𝑎𝑐𝑒 ≪ 𝑅𝑐𝑜𝑛 , 𝑅𝑡𝑟𝑎𝑐𝑒 ≪ 𝑅𝑐ℎൗ2 𝑅𝑡𝑟𝑎𝑐𝑒 could be ignored. Cgs + Cgd
High accuracy. Linearize the parasitic capacitors (Cgd , Cgs ) added them together.
Cgb
Fast execution time. Linearized the parasitic resistor (𝑅𝑐𝑜𝑛 ) then added to 𝑅𝑐ℎൗ2 and 𝑅𝑝𝑜𝑥 .
R pox + R con +
R pox + R con +
d R ch/2
Tackling the convergence problems. b R ch/2
s
A1 A10 A40
Spring-Mass-Damper
Linear Fit
7
K b Model
Measured Error
Error (Latency) [%]
6.5
𝐂𝐠𝐜
Channel Channel
5.5
𝐑 𝐩𝐨𝐱 + 𝐑 𝐜𝐨𝐧
Base Drain
4 4.5
Insulator : 𝐀𝐥𝟐 𝐎𝟑
Substrate : Si
0 5 10 15 20 25 30 35 40
Fig. 1: NEM Relay Structure Based on [1] Number of stages
Number of stages
Table below shows the evaluation of the proposed model in terms of latency, scalability, and simulation time.
Methodology:
Lumped Verilog-A model based NEMS No. of Latency Simulation Time
Mechanical dynamics: spring, damper, mass Circuits Relays Std. Pro. Error(%) Std. Pro. Improvement
Electrical parasitic: capacitor and resistor (%)
Source AND 2 15ns 15.7ns 4.6 3m 4s 2m 23s 23
𝐕𝐒𝐨𝐮𝐫𝐜𝐞 𝟎
𝐙𝟎
2-input C- 10 15ns 16ns 6.0 6m 28s 3m 55s 39
= −𝒌 − 𝒌𝒎
Sequential element
Lumped mechanical parameters
𝐕𝐒𝐨𝐮𝐫𝐜𝐞 𝟏
𝒎
𝐅𝐯𝐝𝐰 𝟏 element
𝑸𝒎
𝐙𝟏 1-bit CRA
Verilog-A
Verilog-A
𝒁
𝒁
𝟎
𝟏
5.9 28
𝑭
Average
𝒆𝒍𝒆. + 𝑭𝒗𝒅𝒘
Conclusion: References:
[1]M. Spencer, F. Chen, et al., "Demonstration of integrated micro-
𝐕𝐒𝐨𝐮𝐫𝐜𝐞
Mechanical Electrica The methodology of simulating the suspended gate NEM Relay could be us on