ASYNC

2014

Conference
Balancing Regularity and Burstiness in New
Computer Systems
Alex Yakovlev, Haider Alrudainy and
Andrey Mokhov
Microelectronics System Design Group, School of EECE,
Newcastle University, UK

{alex.yakovlev, h.m.a.alrudainy, andrey.mokhov}@ncl.ac.uk

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 ASYNC 2014
Conferenc

Outline of presentation:
 Biological systems
 Regular and Bursty operation
 System tear and wear (aging)
 Adiabatic logic based NEM relay
 Future work

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 ASYNC 2014
Conferenc

Outline of presentation:
 Biological systems
 Regular and Bursty operation
 System tear and wear (aging)
 Adiabatic logic based NEM relay
 Future work

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Conference
Biological Systems:
 Regular activities: take place all the time and meant to serve the needs of the
overall system.
 Bursty activities: triggered by or in accordance with the needs to react to the
demands of the environment.

How we could manage to organise their operation in an energy efficient and robust
way ?
 Why not build a computer system in a similar fashion?
 Constantly active part has to be relatively slow.
 Fast processing part has to be done in specialised units (peripheral).

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 ASYNC 2014
Conference
Outline of presentation:
 Biological systems
 Regular and Bursty operation
 System tear and wear (aging)
 Adiabatic logic based NEM relay
 Future work

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 ASYNC 2014
Conference
Regular and Bursty Operation:
 Regular activities are responsible for:
 Power distribution inside the system.
 Communication infrastructure.
 Regular tasks (reference tasks): determine the ‘function face’ of the system in
terms of performance, energy and reliability.
 Highly frequency regular tasks: guaranteed level of performance and timing,
Required clock driven or voltage scaling. Gate power &
Elastic Timing
High Req
 Low frequency regular tasks: frequency
Intensive
Stable ack bursty
regular
implemented by using adiabatic style, Vdd Clock
Power
supply
Core Periphery
to minimise the heat dissipation
Low Req
Loose
during Charging / discharging cycle. Adiabatic
frequency ack bursty
regular
Vdd
5/21/18 power & Clock Elastic power &
Timing
 ASYNC 2014
Conference
Regular and Bursty Operation:
 Bursty or sporadic activities are responsible for:
 Serve the user and/or environment stimuli demands.
 Serve a particular types of computation functions triggered by the
command from the core part (executing instructions).
 bursty tasks (specific tasks):
 Intensive bursty: regulated by the level of supply voltage (timing elasticity).
 Loose bursty: allow maximum elasticity Gate power &
Elastic Timing
High Req
(elastic both in time and voltage level) frequency
Intensive
Stable ack bursty
regular
Vdd Clock
Power
supply
Core Periphery
Low Req
Loose
frequency ack
Adiabatic
regular bursty
Vdd
5/21/18 power & Clock Elastic power &
Timing
 ASYNC 2014
Conference
Outline of presentation:
 Biological systems
 Regular and Bursty operation
 System tear and wear (aging)
 Adiabatic logic based NEM relay
 Future work

5/21/18
 ASYNC 2014
Conference
System tear and wear (aging):
Duty cycle:
 Regular activity: low rate and regular.
 Burst activity: high right and infrequently.
How to balance the activity in the core and peripheral parts, which intuitively helps
the overall system to age gracefully and uniformly.
Regular tasks frequency=
Bursty task frequency =

5/21/18
 ASYNC 2014
Conference
Outline of presentation:
 Biological systems
 Regular and Bursty operation
 System tear and wear (aging)
 Adiabatic logic based NEM relay
 Future work

5/21/18
 ASYNC 2014
Conference
Adiabatic logic based CMOS:
 Adiabatic logic family: Energy charge recovery(ECRL), T T T

positive feedback (PFAL), 2N-2P, 2N-2N2P, pass

transistor (PTAL), clocked adiabatic logic (CAL). Out
 Principle: if the voltage in a circuit changes slower F F

than the electric time constant, then resistive losses Energy charge recovery logic based CMOS
are reduced (less heat dissipate). R i(t)
C
 How to eliminate the leakage current during the
evaluate, hold, and recovery stage?
T
 The energy dissipated in a complete charge-
discharge clock cycle:
+0.5C

Energy VS frequency based AL [1]

 ASYNC 2014
Conference

Adiabatic logic based NEMS:

 This analysis based on the suspended gate NEM relay [2].

g
 The energy dissipated in a complete charge-discharge clock cycle:

Out

2 Input F F

= 0.5 (
Energy charge recovery based NEMS
+ 0.5 (

,s

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Suspended gate NEM relay [2]
 ASYNC 2014
Conference
 At 90 nm, NEM relay has the below specifications as shown in Table I [2].
 CMOS technology parameters from predictive technology model as shown in Table II [3]
 Energy VS frequency of buffer based ECR adiabatic logic shown in Table III

Table II: CMOS technology parameters from predictive model Table III: Energy VS frequency
Frequency NEMS CMOS
Parameter
kΩ. m fF/m μA (MHz) Energy energy
5 1156.2 15 pj
CMOS 1.6 2.2 0.5 0.18 150
10 1160.5 7.5pj

Table I: Scaled NEM relay parameter. 20 1169 3.75pj

Parameter Pitch 50 1194.6 1.5pj
50 1.5pj
Scaled 2k 6fF 0.5V 0.3 V 20 80
80 1220.9 0.937pj
0.937pj
NEMS
100
100 1237.2 0.75pj
0.75pj
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 Limitation of NEM relay based adiabatic logic:
 Mechanical Delay Impact:
 failure happened
 , act like static
 adiabatic effect happened

 Power clock generators (PCGs):

 Consuming a large portion of the total
 Routing multiple clock phases raise a cost, performance and viability issues.

 To design more energy efficient adiabatic logic based NEM relay, we can postulate:

 Designing of asynchronous adiabatic logic based on NEM relay: it could be possible to

produce a logic design methodology that is only active when it is performing useful
computation, and recycles a large proportion of the energy used to perform those
computations.

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Conference
S1 S2 S3 S4
Adiabatic Adiabatic Adiabatic Adiabatic
NEM relay NEM relay NEM relay NEM relay

C&R C&R C&R

Control Signal

S1 S2 S3 S4
Adiabatic Adiabatic Adiabatic Adiabatic
NEM relay NEM relay NEM relay NEM relay
c

c
R1 R2 R3 R4
CD CD CD CD
Ack
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 Future work
References:
[1] Teichmann, P.: Adiabatic Logic: Future Trend and System Level Perspective.
Springer,
Dordrecht (2012).
[2] M. Spencer, F. Chen, C. C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, et al.,
"Demonstration of integrated micro-electro-mechanical relay circuits for VLSI
applications," IEEE Journal of Solid-State Circuits, vol. 46, pp. 308-320, // 2011.
[3] Predictive Technology Models, http://ptm.asu.edu

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