CIRCUIT

PARTITIONING
MADE BY-
ISHA SATYAKAM,
ROLL NO:0709122026
IC,FINAL YEAR.
WHAT IS PARTITIONING?

The process of decomposition of a complex

system into a set of smaller, simpler subsystems,
is called PARTITIONING.
NEED FOR PARTITIONING

 Efficient designing of any complex system

necessitates its decomposition into a set of
smaller subsystems.
 Each subsystem is then designed
independently and simultaneously to speed
up the design process.
STEPS OF PARTITIONING

 Decompose a large complex system into

smaller subsystems
 Decompose hierarchically until each
subsystem is of manageable size
 Design each subsystem separately to speed
up the process
 Minimize connection between two
subsystems to reduce interdependency
PARAMETERS FOR ENHANCING
PARTITIONINIG EFFICIENCY

 System must be decomposed carefully so

that the original functionality of the system
remains intact.
 System decomposition should ensure
minimization of the interface connections
between any two subsystems.
 Time for decomposition should be a small
fraction of the total design time.
APPLICATIONS OF PARTITIONING

 Design of computer system in general, and

VLSI chips in particular.
Computer system is composed of tens of
millions of transistors. It is partitioned into
several smaller modules/blocks for ease in
designing.
Each block has terminals located at the
periphery that are used to connect the
blocks.
The connection is specified by a net-list ,
which is a collection of nets.
A net is a set of terminals which have
to be made electrically equivalent.
PARTITIONING AT VARIOUS
LEVELS
PARTITIONING LEVELS

SYSTEM LEVEL PARTITIONING:

The partitioning of a system into a group of
PCBs is called the system level partitioning.
BOARD LEVEL PARTITIONING:
The partitioning of a PCB into chips is called
The board level partitioning.
CHIP LEVEL PARTITIONING:
The partitioning of a chip into smaller sub-circuits is
called the chip level partitioning.
SYSTEM LEVEL PARTITIONING

The circuit assigned to a PCB must satisfy

certain constraints .Each PCB has a fixed area,
and a fixed number of terminals to connect with
other boards.
The total number of such terminals is called the
terminal count of the board.
The sub-circuit allocated to a board must be manufacturable within
the board dimensions.
The number of nets used to connect this board to the other boards
must be within the terminal count of the board.
BOARD LEVEL PARTITIONING

Board level partitioning ventures to minimize

the area of each chip.
The cost of manufacturing a chip is proportional
to its area.
The number of chips used for each board must
be minimized for enhanced board reliability.
CHIP LEVEL PARTITIONING

The circuit assigned to a a chip can be

fabricated as a single unit, therefore partitioning
at this level is necessary.
A chip can accommodate as many as three
million or more transistors.
The objective of chip level partitioning is to
facilitate efficient design of the chip.
PARTITIONING PROBLEM

Objective:
 Minimize interconnections between partitions
 Minimize delay due to partitioning
Constraints:
 Number of terminals in each subsystem (Count (Vi) <
Ti)
 Area of each partition (Aimin < Area(Vi) < Aimax)
 Number of partitions (Kmin < k < Kmax)
 Critical path should not cut boundaries
DESIGN STYLE SPECIFIC
PARTITIONING PROBLEMS

 Full custom design style:

Partitions can be of different sizes and hence there are
no area constraints for the partitioning algorithms.
 Standard cell design style:
Partition the circuit into a set of disjoint sub-circuits
such that each sub-circuit corresponds to a cell in a
standard cell library.
 Gate array design style:
The circuit is bi-partitioned recursively until each resulting partition
corresponds to a gate on the gate array.
CLASSIFICATION OF PARTITIONING
ALGORITHMS

On availability of initial partitioning:

1. Constructive algorithms and
2. Iterative algorithms.
On the nature of the algorithms:
1. Deterministic algorithms and
2. Probabilistic algorithms.
On the basis of the process used for
partitioning:
1. Group Migration algorithms,
2. Simulated Annealing and Evolution based algorithms and
3. Other partitioning algorithms.
CONSTRUCTIVE & ITERATIVE
ALGORITHMS

Constructive algorithms:
The input comprises the circuit components
and the net-list while the output is a set of
partitions and the new net-list. Constructive
algorithms are used as pre-processing
algorithms for partitioning.
Iterative algorithms:
Accept a set of partitions and the net-list as input and
generate an improved set of partitions with the modified
net-list.
DETERMINISTIC & PROBABILISTIC
ALGORITHMS

Deterministic algorithms:
Produce repeatable or deterministic solutions.
For example, an algorithm using deterministic
functions, always generates the same solution
for a given problem.
Probabilistic algorithms:
Capable of producing a different solution for the same
problem each time they are used, as they make use of
some random functions.
GROUP MIGRATION,SIMULATED
ANNEALING & EVOLUTION BASED
ALGORITHMS

Group Migration algorithms:

They start with some partitions, generated
randomly, and then move components between
partitions to improve the partitioning.
Simulated Annealing/Evolution:
They use a cost function, which classifies any feasible
solution and a set of moves ,which allows movement
from solution to solution. These algorithms are
computationally intensive as compared to others.
KERNIGHAN-LIN ALGORITHM
 Input: Graph representation of the circuit.
 Output: Two subsets of equal sizes.
 Bisecting algorithm :
● Initial bisection.
● Vertex pairs which gives the largest decrease in
cut-size are exchanged.
● Exchanged vertices are locked.
● If no improvement is possible and some vertices
are still unlocked then vertices which give smallest
increase are exchanged.
PERFORMANCE DRIVEN
PARTITIONING

With the advent of the high performance chips, the on-chip delay
has been greatly reduced. Typically , on-chip delay is in the order
of few nanoseconds while on-board delay is in the order of a
few milliseconds. The design of high performance system requires
partitioning algorithms to reduce the cut-size as well as to
minimize the delay in critical paths. The partitioning algorithms,
dealing with such high performance circuits are called as timing
(performance) driven partitioning algorithms and the process is
called as performance driven partitioning.