UNIT-V

INTERRUPT STRUCTURE OF 8086

• While the CPU is executing a program, an interrupt breaks the
normal sequence of execution of instructions, diverts its
execution to some other program called “Interrupt Service
Routine (ISR).

• After executing ISR, the control is transferred back again to the

main program which was being executed at the time of
interruption.

• Nested interrupts.

• In 8086, there are two interrupts pins: 1. NMI 2. INTR

• NMI :-- Non Maskable Interrupt input pin which means that any
interrupt request at NMI input cannot to masked or disabled by
any means.

• INTR:-- It can be masked using the Interrupt Flag (IF).

• If more than one type of INTR interrupt occurs at a time, then
an external chip called programmable interrupt controller is
required to handle them. (eg: 8259 interrupt controller).

• There are two types of interrupts

1. External interrupts
– These interrupts are generated by external devices i.e out
side the processor (uing NMI, INTR pins). Eg: Keyboard
interrupt.

1. Internal interrupts
– It is generated internally by the process circuit or by the
execution of an interrupt instruction. Eg: INT instruction,
overflow interrupt, divide by zero. At the end of each
instruction cycle, the 8086 checks to see if any interrupts
have been requested.
 8086 Interrupt Vector Table
– The first 1Kbyte of memory of 8086 (00000 to 003FF) is set
aside as a table for storing the starting addresses of
Interrupt Service Procedures (ISP).

– Since 4-bytes are required for storing starting addresses of

ISPs, the table can hold 256 Interrupt procedures.

– The starting address of an ISP is often called the Interrupt

Vector or Interrupt Pointer. Therefore the table is
referred as Interrupt Vector Table.

– In this table, IP value is put in as low word of the vector &

CS is put in high vector.
8259 – Interrupt controller
 8259A Internal Architecture
1. Interrupt Request Register (IRR):-
– The interrupts at IRQ input lines are handled by IRR internally. IRR stores
all the interrupts in it, in order to serve them one by one on the priority
basis.

2. In-Service Register (ISR):-

This register stores all the interrupt requests those are being served, i.e ISR
keeps a track of the requests being served.

3. Priority Resolver:-
This unit determines the priorities of the interrupt requests appearing
simultaneously.
The highest priority is selected & stored into the corresponding bit during
INTA pulse.
IR0 - highest priority
IR7 - lowest priority ; in fixed priority.
4. Interrupt Mask Register (IMR):-
This register stores the bits required to mask the
interrupts inputs. IMR operates on IRR at the direction
of the Priority Resolver.

5. Interrupt Control logic:-

– This block manages the interrupt and interrupt
acknowledge signals to be sent to the CPU for serving
one of the 8 interrupt requests.

– This also accepts the interrupt acknowledge (INTA)

signal from CPU that causes the 8259A to release vector
address on to the data bus.
6. Data Bus Buffer:-

– This Tri-state bidirectional buffer interfaces internal 8259A bus the

microprocessor data bus.

– Control words, status & vector information pass through data buffer
during read or write operations.

7. Read/Write Control logic:-

– This circuit accepts and decodes commands from the CPU. This block also
allows the status of the 8259A to be transferred on to the data bus.
8. Cascade Buffer/Comparator:-

– This block stores & compares the IDs of all the 8259As
used in the system.

– The 3 I/O pins CAS0 – CAS2 are outputs when the 8259A
is used as a master.

– The same pins used as inputs when it is in the slave mode.

– 8259A in master mode, sends the ID of the interrupting

slave device on these lines. In slave, will send its pre-
programmed vector address on the data bus during the
next INTA pulse.
Interrupt Sequence in an 8086 system

1. One or more IR lines are raised high that set corresponding IRR bits.

2. 8259A resolves priority and sends an INT signal to CPU.

3. The CPU acknowledges with INTA pulse.

4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is
set and the corresponding IRR bit is reset. The 8259A does not drive data
bus during this period.

5. The 8086 will initiate a second INTA pulse. During this period 8259A
releases an 8-bit pointer on to data bus from where it is read by the CPU.

6. This completes the interrupt cycle. The ISR bit is reset at the end of the
second INTA pulse if automatic end of interrupt (AEOI) mode is
programmed. Otherwise ISR bit remains set until an appropriate EOI
command is issued at the end of interrupt subroutine.
Command Words of 8259A
• The command words of 8259A are classified in two groups
1. Initialization Command Words (ICWs)
2. Operation Command Words (OCWs)

Initialization Command Words (ICWs):-

• Before starts functioning, the 8259A must be initialized by writing two to
four command words into the respective command word registers. These
are called as Initialization Command Words (ICWs).

• If A0 =0 and D4=1, the control word is recognized as ICW1.

• It contains the control bits for edge/level triggered mode, single/cascade
mode, call address interval and whether ICW4 is required or not, etc.

• If A0 =1, the control word is recognized as ICW2.

 It stores details regarding interrupt vector addresses.
Once ICW1 is loaded, the following initialization procedure is
carried out internally.
a) The edge sense circuit is reset, i.e by default 8259A interrupts
are edge sensitive
b) IMR is cleared
c) IR7 input is assigned the lowest priority
d) Slave mode address is set to 7
e) Special mask mode is cleared and the status read is set to IRR
f) If IC4 =0, all the functions of ICW4 are set to zero . Master/slave
bit in ICW4 is used in the buffered mode only.
ICW1 , ICW2 ---- are compulsory
ICW3 , ICW4 -- are optional.
 ICW1

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 A7 A6 A5 1 LTIM ADI SNGL IC4

1=ICW4 Needed
0= No ICW4 Needed

A7-A5 of interrupt vector address

MCs 80/85 mode only 1=Single
Don’t care to 8086 0= Cascaded

Call Address Interval

1=Interval of 4 bytes
1=Level triggered
0= Interval of 8 bytes
0= Edge triggered
ADI=1 for 8086 based system
 ICW2

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 T7 T6 T5 T4 T3 A10 A9 A8

For 8085 system:

T7-T3 : they are filled by A15-A11 of the Interrupt Vector Address
A10-A8: these bits are same as the respective bits of vector address

For 8086 system:

T7-T3 : Interrupt type
A10-A8: 3 bits are 0, pointing to IR0.
 ICW3
a) Master Mode: SP=1, in buffer mode M / S =1 in ICW4

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 S7 S6 S5 S4 S3 S2 S1 S0

Sn = 1  IRn input has a slave

Sn = 0  IRn input does not have a slave

b) Slave Mode: SP=0, in buffer mode M / S = 0 in ICW4

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 ID2 ID1 ID0

ID2-ID0  000 to 111 for IR0-IR7 i.e slave1 to slave8

 ICW4

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 SFNM BUF M/S AEOI mPM

0= 8085 system operation

1= 8086 system operation

SFNM=1 : Specially Fully 1= Automatic End of

Nested Mode is selected Interrupt Mode is
selected

1= 8259 is Master
1= Buffered mode 0= 8259 is slave
0= Un buffered mode If BUF=0, M/S is neglected
 Operation command words (OCWs)

• Once ICW registers (accepting the interrupts) are initialized, 8259

is ready for its normal function.

• 8259 has its own ways of handling the received interrupts called
as modes of operation. These can be selected by programming i.e
writing 3 OCW registers.

• OCW1: It is for mask the unwanted interrupt requests.

• OCW2: It controls the end of interrupt, the rotate mode and their
combination

• OCW3: It is for set or reset for special mask mode

0
0
ISR
 Operating Modes of 8259
• Fully Nested Mode
– This is the default mode of operation of 8259A.

• End of Interrupt (EOI)

1. Specific EOI
Determines which ISR bit is to be reset on EOI
2. Non-Specific EOI
Automatically reset the highest ISR bit out of those already set.

• Automatic Rotation
– This is used in the applications where all the interrupting devices are
of equal priority.

• Automatic EOI Mode

– Till AEOI=1 in ICW4, the 8259A operates in AEOI mode.
– In this mode, the 8259 performs a non-specific EOI operation at the
trailing edge of the last INTA pulse automatically.
• Specific Rotation
– In this mode a bottom priority level can be selected, using
L2,L1, L0 in OCW2 and R=1,SL=1, EOI=0.
– If IR5 is selected as a bottom priority , then
IR5 --- 7
IR4 --- 6

IR0 --- 2

• Special Mask Mode

– When a mask bit is set in OCW, it inhibits further
interrupts at that level & enables interrupt from
other levels which are not masked.
• Edge & Level triggered mode
– LTIM=0 edge triggered
– LTIM=1 level triggered in ICW1

• Reading 8259 status

– OCW3 is used to read IRR & ISR while OCW1 is used to
read IMR. Reading is possible only in no polled mode.

• Poll command
– In this mode, the INT output is neglected.
– The poll mode is entered by setting P=1 in OCW3. The
8259A is polled by using software execution by µp instead
of the requests on INT input. It is not used in 8086.
• Special Fully Nested Mode (SFNM)
– This mode is used in more complicated systems, where cascading is used and
the priority has to be programmed in the master using ICW4.

– In this mode the master interrupts the µp only when the interrupt device has
a higher or the same priority than the one currently being served.

• Buffered Mode
– When the 8259A is used in the systems in which bus driving buffers are used
on data buses (e.g. cascade systems) the problem of enabling the buffers
arises. The 8259A sends a buffer enable signal on SP / EN pin whenever data
is placed on the bus.

• Cascade Mode
– The master controls the slaves using CAS0-CAS2 which act as chip select
inputs for slave. In this mode, the slave INT output are connected with
master IR inputs. EOI issued twice one for master other for slave.
 Interfacing 8259A with 8086
A9
A8
A7
A6
A10
+Vcc

G1
G2 G3
M/IO A5 A4
A2 74LS IR0
A3 CS
A1 138 Y0 IR1
A2 A0 IR2
8086 WR WR IR3
RD RD 8259
IR4
INTA INTA IR5
INTR INT IR6
A1 A0 IR7
D0-D7
GND
 Interfacing and Programming 8259
Problem:
Show 8259A interfacing connections with 8086 at the address 07x.
Write an ALP to initialize the 8259A in single level triggered mode, with
call address interval of 4, non-buffered, no special fully nested mode.
Then set the 8259A to operate with IR6 masked, IR4 as bottom priority
level, with special EOI mode. Set special mask mode of 8259A. Read IRR
and ISR into registers BH and BL respectively. IR0 of 8259 will have type
80h.

1. ICW1 ( to set single mode, address interval of 4, level triggered

mode, ICW4 is needed)
A0 D7 D6 D5 D4 D3 D2 D1 D0
ICW1 = 0 0 0 0 1 1 1 1 1 = 1Fh

2. ICW2 (to select IR0)

A0 D7
ICW2 = 1 1 0 0 0 0 0 0 0 = 80h
3. ICW3  Not needed , because 8259 is in single mode.
4. ICW4 (to select 8086 system)
A0 D7
ICW4 = 1 0 0 0 0 0 0 0 1 = 01h

5. OCW1 (to mask IR6)

A0 D7
OCW1 = 1 0 1 0 0 0 0 0 0 = 40h

6. OCW2 (to set Specific EOI with Rotating Priority, IR4 is Bottom priority)
A0 D7
OCW2 = 0 1 1 1 0 0 1 0 0 = E4h

7. OCW3 (to set Special Mask Mode, and read IRR, ISR)
A0 D7
a) OCW3 = 0 0 1 1 0 1 0 1 0 = 6Ah (to read IRR)
b) OCW3 = 0 0 1 1 0 1 0 1 1 = 6Bh (to read ISR)
ALP program:
CODE SEGMENT
ASSUME CS:CODE

START:
MOV DX, 0070h
MOV AL, IFh ; for ICW1
OUT DX, AL

MOV DX, 0702h ; for ICW2

MOV AL, 80h
OUT DX, AL

MOV AL, 01h ;for ICW4

OUT DX, AL

MOV AL, 40h ; for OCW1

OUT DX, AL
MOV AL, 0E4h ; for OCW2
MOV DX,0740
OUT DX, AL

MOV AL, 6Ah ; for OCW3

OUT DX, AL

MOV AL, 6Bh ; for OCW3

OUT DX, AL

IN AL,DX
MOV BH,AL
MOV AH,4Ch ;Return to DOS
INT 21H

CODE ENDS
END START
 DOS & BIOS Interrupts

BIOS Interrupts

I. INT 16h :- for Keyboard Input

These interrupts include reading a character from keyboard &
getting the status of the keyboard.

1. Function 10h:- (Read keyboard character)

• This standard keyboard operation checks the keyboard buffer
for an entered character.
• If none is present, it waits for the use to press a key. If a
character is present, the ASCII code of the key is returned to AL
& its scan code to AH register.
Eg:
MOV AH,10h
INT 16h
CMP AL, ‘Y’
JE Enter
• The key pressed is not shown on the screen.

2. Function 11h:- (Determine if character is present)

• If the character is present in the keyboard buffer, this

operation clears the ZF returns the character to AL & its scan
code to AH & character remains in the buffer.
• If no character is present, the operation sets the ZF & does
not wait for a key like the function 10h.
II. INT 10h :- for Video Services
BIOS INT 10h supports many services to facilitate

1.Function 00h :- (Set video mode)

A video made scan be text mode or graphics mode. The

generally used video mode is 25 rows X 80 columns, color, text
mode .
To set a mode we have to load function code in to AH & mode
number into AL.
Ex:
MOV AH,00h ; loading function code
MOV AL, 03h ; standard color text.
INT 10h ; call interrupt service routine.
2. Function 05h :- ( select active page)
Function 05h lets you select the page that is to be displayed in text or graphics
made.
We can create new pages & request alternating between pages
Eg:
MOV AH, 05H ; Request active page
MOV AL ,00h ; page 0 is selected
INT 10h

3. Function 02h :- (Set cursor position)

This function is used to set the cursor position anywhere on the screen.
The Row no. & Column no. are given in DH & DL registers & the BH register
should contain the page no.
Eg:
MOV AH, 02h ; request to set cursor
MOV BH, 00h ; page 00h
MOV DH, 16 ; Row=16
MOV DL, 32 ; Column=32
INT 10h
4. Function 03h :- ( Return curser status)

This function is used to determine the position of curser & the

size of the curser. The page No. has to be mentioned in BH
register.

Ex:
MOV AH, 03h ; Request curser location
MOV BH, 00h ; Page No: is 0
INT 10h

Out put : DH: row No.

DL; column No.
CH : Starting Scan time
CL : Ending Scan time.
5. Function 09h : ( Display character & Attribute)

This operation displays specified No. of characters on the screen accordingly

to the given attribute.

The character is displayed at the current position of cursor.

AL ----- ASCII character
BL ----- Attribute value
BH ---- Page No.
CX --- count

Ex: The following code prints ten Ts

MOV AH, 09h ; Request Display

MOV AL, ‘T’ ; T to be displayed
MOV BH, 00h ; page 0
MOV BL, 02 h ; black back-ground & green fore ground
MOV CX , 0A h ; counter ( ie. 10’T’s)
INT 10h
DOS Interrupts
INT 21h :-

1. Function 01h :- (keyboard input with Echo)

– This is similar to INT 16h’s 10h function but this
function displays keyboard & does not return scan
mode.
– After the interrupt ; we have ASCII code in AL
– To get a scan code for this key in AL, we should repeat
INT 21h immediately.
Ex:
MOV ah, 01H ; Request keyboard input
INT 21h
2. Function 07h :- (Keyboard input without Echo)

It is like function 01h, except that it doesn’t echo the key

onto the display.
This is useful for accepting passwords that are to be
invisible.

Eg:
MOV AH, 07h ; request keyboard input
INT 21h

3. Function 0Bh :- (check keyboard status)

- This operation returns FFh in AL if input character is
available in the keyboard buffer
- 00h if no character is available. This doesn’t wait for the
user to press the key.
4. Function 02h :- (Screen display)

- This is useful for displaying single characters.

DL – character
Ex:
MOV AH, 02h ;request character display
MOV DL, ‘S’
INT 21h

5. Function 09h :- (Displaying strings)

- This function requires the string to be displayed to end with a ‘$’

sign.
Ex:
String DB “Enter your name: $”
MOV AH, 09h ; request display
LEA DX, String ; load address
INT 21h