MODULE 1

Architecture of 8086
8086 PIN DIAGRAM
PHYSICAL MEMORY ORGANIZATION
MINIMUMMODE 8086 SYSTEM
READ CYCLE TIMING DIAGRAM
WRITE CYCLE TIMING DIAGRAM
BUS REQUEST AND BUS GRANT
TIMINGS
MAXIMUM MODE 8086 SYSTEM
MEMORY READ TIMING IN MAXIMUM
MODE
MEMORY WRITE TIMING IN
MAXIMUM MODE
MODULE 2
INTERRUPT VECTOR TABLE
8259 ARCHITECTURE
PIN DIAGRAM -8259
MODULE 4
8255 ARCHITECTURE
8255 PIN DIAGRAM
8279 ARCHITECTURE
8257 ARCHITECTURE
MODULE 5
8051 ARCHITECTURE
PIN DIAGRAM
MODULE 6
8254/8253 ARCHITECTURE
8254/53 PIN DIAGRAM