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Instruction Set Architecture (ISA) : ISA Level Elements of Instructions Instructions Types Number of Addresses Registers Types of Operands
Instruction Set Architecture (ISA) : ISA Level Elements of Instructions Instructions Types Number of Addresses Registers Types of Operands
Instruction Set Architecture (ISA) : ISA Level Elements of Instructions Instructions Types Number of Addresses Registers Types of Operands
operations
e.g. ADD, SUB, LOAD
instructions
Operands can also be represented symbolically
ADD A,B
Simple Instruction Format
Instruction Types
Data processing – Arithmetic and logic
instructions
Data storage (main memory) – memory
instructions
Data movement (I/O) – I/O instructions
Control (Program flow control) – Test
and branch instructions
Number of Addresses
Number of addresses per instructions can describe processor
architecture
3 addresses
Operand 1, Operand 2, Result (Destination)
May be a forth address - next instruction (usually implicit, obtained
from PC)
Example below: T=temporary location used to store intermediate
results
Not common in use
Needs very long words to hold everything
Number of Addresses
2 addresses
One address doubles as operand and
result(destination)
Reduces length of instruction and space requirements
More registers
Fewer addresses
Less complex (powerful?) instructions
Operation repertoire
How many ops?
What can they do?
How complex are they?
Data types
Instruction formats
Length of op code field
Number of addresses
Instruction Set Design Decisions (2)
Registers
Number of CPU registers available
Which operations can be performed on
which registers?
Addressing modes (later…)
RISC v CISC
Registers (32-bit)
31 0
eax ‘A’ register
ebx ‘B’ register
ecx ‘C’ register
edx ‘D’ register
esi source index register
edi destination index register
esp sp
ebp bp
Pentium Registers & Addressing
K.K. Leung Fall 2008 Modes 17
…Registers (8-bit)
31 1615 0 15 87 0
eax ax ah al
ebx bx bh bl
ecx cx ch cl
edx dx dh dl
The 2 least significant bytes of registers eax, ebx, ecx and edx also
have register names, that can be used for accessing 8 bits.
The instruction pointer register eip holds the address of the next
instruction to be executed. The eip register corresponds to the
program counter register in other architectures.
32-bit eflags
The eflags register holds information about the current state of the CPU. Its
32-bits are mostly of interest to the Operating System; however, some of its
bits are set/cleared after arithmetic instructions are executed, and these bits
are used by conditional branch instructions:
Logical Data
Bits or flags
Example: Types of Operand for
Pentium 4
Module 3
Instruction Set Architecture (ISA):
Addressing Modes
Instruction Formats
Addressing Modes
Addressing – reference a location in
main memory/virtual memory
Immediate
Direct
Indirect
Register
Register Indirect
Displacement (Indexed)
Addressing
Modes
A=contents of an address field
in instruction
(X)=contents of memory
location X or register X
Addressing Modes
Immediate Addressing
Operand is part of instruction
Operand = A
e.g. ADD EAX,5
Add 5 to contents of register EAX
5 is operand
Operand
Indirect Addressing (1)
Memory cell pointed to by address field
contains the address of (pointer to) the
operand
EA = (A) or EA = [A]
Look in A, find address (A) and look there
for operand
e.g. ADD EAX,(A) or ADD EAX,[A]
Add contents of cell pointed to by contents
of A to register EAX
Indirect Addressing (2)
Large address space
2n where n = word length
May be nested, multilevel, cascaded
e.g. EA = (((A))) or EA = [[[A]]]
Draw the diagram yourself
Multiple memory accesses to find
operand
Hence slower
Indirect Addressing Diagram
Instruction
Opcode Address A
Memory
Pointer to operand
Operand
Register Addressing (1)
Operand is held in register named in
address filed
EA = R
Limited number of registers
Very small address field needed
Shorter instructions
Faster instruction fetch
Register Addressing (2)
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming or
compiler writing
c.f. Direct addressing
Register Addressing Diagram
Instruction
Opcode Register Address R
Registers
Operand
Register Indirect Addressing
C.f. indirect addressing
EA = (R) or EA = [R]
Operand is in memory cell pointed to by
contents of register R
Large address space (2n)
One fewer memory access than indirect
addressing
Register Indirect Addressing
Diagram
Instruction
Opcode Register Address R
Memory
Registers
Registers
Memory organization
Bus structure
CPU complexity
CPU speed