Switched Capacitor DC-DC

Converters: Topologies and

Applications
Bill Tsang and Eddie Ng
Outline
Motivations
Dickson’s Charge Pump
Other Various Charge Pumps
Applications
Conclusion
Motivations
Inductorless
On-chip integration
Low cost
High switching frequency
Easy to implement (open-loop system)
Fast transient but large ripple
High efficiency but limited output power
Ideal Dickson’s Charge
Pump(Phase 1)
2VDD-Vt
VDD
VDD-Vt

VDD-Vt
VDD Vo

VDD-Vt C1 C2 C3

clk
0
clk_bar
VDD

• Clk=0, Clk_bar=VDD
• Finite diode voltage drops, Vt
Ideal Dickson’s Charge
Pump(Phase 2)
3VDD-2Vt
VDD 2VDD-Vt
2VDD-2Vt
VDD-Vt

VDD Vo

VDD-Vt C1 C2 C3

clk
VDD
clk_bar
0

• Clk=VDD, Clk_bar=0
• Maximum voltage stress on diodes 2VDD-Vt => reliability issue
• Maximum voltage stress on capacitors VCn =n(VDD-Vt) => reliability issue
Dickson’s Charge Pump
V2+dV2
V1+dV1

V2
V1 V
Vth

v1 v2
VDD Vo

Cp C1 Cp C2 Cp C3

clk C1=C2=C3=C
clk_bar

C Io
V  V 
C  C p f (C  C p )
V  Vth (Body effect can be significant at later stages)

Vout  VDD  N * (V  Vt )  Vt

Non-idealities
Threshold voltage drop [Mos charge pumps for low-voltage operation]


Vth  Vtho  γ VBS  2φF  2φF 
Parasitic capacitor divider voltage drop
Low conversion efficiency and pumping
gain G  V  V  V  V (V )
V2 2 1 tn 2
Limited maximum number of stages
2
 VDD  Vtho 
Vout,max    2φF   2φF
 γ  [An on-chip High-voltage generator circuit for
EEPROMs with a power supply voltage below 2V]
Modified Switch
MD1 MD1

VDD VDD

MS1

2VDD
CTS

clk
clk

•Static Charge Transfer Switches (CTS)

•Eliminate transistor threshold drop
Modified Dickson’s Charge Pump #1 (NCP-1)
dV
v3
dV
V2
dV
v1

MD1 MD3 MD4

MD2
v1 v2 v3 Vo
VDD

MS1 MS2 MS3 MS4

Cp
Cp
Cp C1 Cp C2 Cp C3 C4 C5

clk

clk_bar

Conditions:
1, Clk=Vdd,Clk_bar=0: v2, v3+V
To turn on transistor Ms2; Vgs = 2V 2 * V  Vtn (V2 )
2, Clk=0,Clk_bar=VDD: v1, v2+V,v3
To turn off transistor Ms2; Vgs = 2V 2 * V  Vtn (V1 ) impossible
Modified Dickson’s Charge Pump #1
(NCP-1)
Static Charge Transfer Switches (CTS)
Better voltage pumping gain than diodes
GV 2  V2  V1  V
Lower voltage equals upper voltage of
pervious stage
Utilizing higher voltage from following stage
to drive CTS
Reverse charge sharing since CTS cannot turn
off completely
 Modified Switch #2
MD1

MS1

MN1 used to turn off MS1 MP1 used to turn on MS1

MN1 MP1
Next
stage

clk

• Eliminate transistor threshold drop

• Complete turn-off of switch, MS1
Modified Dickson’s Charge Pump #2 (NCP-2)
dV

dV

dV

MD1 MD3
MD2
v1 v2 v3

MS1 MS2 MS3

MN2 MP2

Cp C1 Cp C2 Cp C3

clk

clk_bar

Conditions:
1, Clk=Vdd,Clk_bar=0: v2, v3+V
To turn on transistor MP2 and MS2; Vgs = 2V 2 * V  Vtp 2 * V  Vtn (V2 )
2, Clk=0,Clk_bar=VDD: v1, v2+V,v3
To turn on transistor MN2 and turn off MS2; Vgs = 2V 2 * V  Vtn (V1 )
Complete Circuit(NCP-2)
dV

dV

dV

MD1 MD3 MD4

MD2
v1 v2 v3
Vo

MS1 MS2 MS3 MS4

q
MN2 MP2

Cp
Cp
Cp C1 Cp C2 Cp C3 C4 C5

clk

clk_bar

•Careful PMOS well connection to prevent latch-up

•Diode-connected output stage used
Modified Dickson’s Charge
Pump #3 (NCP-3)
NCP-3 uses boosted clock at output stage
dV

dV

dV

MD1 MD3 MD4

MD2
Vi
Vo

MS1 MS2 MS3 MS4

q
C5 HV
Clock
Generator

clk
Cp
Cp C1 Cp C2 Cp C3 C4

clk

clk_bar
Converters Output Voltage
Results
Optimum Capacitance
Selection
Ci I out
V  VDD  Vout  VDD  N * V
Ci  C p f (Ci  C p )

Ctot  N * Ci 
C  C V
i p out  VDD 
Ci
CiVDD  I out / f

Ctot 2Ci  C p CiVDD  I out / f   Ci Ci  C p VDD 

 (Vout  VDD )
Ci CiVDD  I out / f 2

2
I out  I out  C p I out
Ci ,min     
VDD f  VDD f  VDD f

[A Low-Ripple Switched-Capacitor DC-DC Up converter for Low-voltage applications]

Efficiency and Output Impedance
Power loss due to: Vth, Rds(on), ESR, Cp,
etc [Performance limits of switched-capacitor DC-DC Converter]

Efficiency estimation
Vout
 M=ideal conversion ratio
M *Vin

Output impedance (slow switching)

[Performance limits of switched-capacitor DC-DC Converter]

 i  Ts Ts=switching period
i= parasitic time constant
 Vout 1
Ro   q=charge supplied to the source Vout
q / Ts fC
 Cross-Coupled Charge Pump
VDD
2Vdd RL
Vo  M10 M9

RL  Rds( on)

I  1 1 
Vripple  L   
2f  CL C1  CL 
Vo
1
Vo  1 
  sC1  sC L  
I L 
C2
RL  C1 RL CL1

phi2
phi1

• PMOS to transmit 2VDD to output

• Bodies tied to source(highest voltage) to
avoid forward biasing junction diodes
[Area-efficient CMOS Charge Pumps for LCD Drivers]
H-bridge Topology
Commercial 1 2

products (Linear
Technology,
Fairchild, Maxim …)
Buck or Boost
functions
3 4

Negative voltage
generation
Oscillator and Control
H-bridge Topologies
Vin
1 2

Phase 1: transistors in red are on

Phase 2: transistors in blue are on Vin

3 4
Vout

1 2
phi1 doubler phi1
phi2 phi2

Vout = 2Vin
Vout
Vin
1 2

3 4
Vin Vout

phi1 inverter phi1

phi2 phi2

3 4
Vin

Vout = -Vin phi1 Splitter phi1

phi2 phi2

Vout = 0.5 Vin

Application (1): Flash Memory
Floating gate programming
Control gate voltage >> Vdd

[ee141 lecture]
Application (1): Flash Memory
Nominal VDD= 5V
Application (2): Sample Switches vicm vicm

phi2d phi1 Ci

Vi+ CL
phi1d phi2
Cs

S/H circuit– constant

+ - Vo+

OTA

vgs sampling with all

- + Vo-
phi1d Cs phi2
Vi- CL

input level
phi2d phi1
Ci

vicm vicm

Reduces distortion VDD

Reduces Rds(on)
M10 M9 A Phi_bar
M4
M5
M8

M3
M7
C1 C2 C3
Voltage
doubler M2

Phi M1
M6 M11
M9
Vo

VSS
Phi_bar
Vin
Application (3): Low voltage
Amplifier
Positive zero in
Miller compensation
1/gm pole-zero VDD

cancellation [charge-pump assisted

low-power/low-voltage CMOS Opamp Design]
Charge pump

V- V+
>2VGS
Conclusion
Different Dickson’s SC converters
discussed
Optimal Capacitor size selection
Discussion of cross-coupled doublers
Commercial product: Full H-bridge
Applications: Flash, ADC, Amplifier, LCD
driver