Professional Documents
Culture Documents
Nowick 2
Nowick 2
Mixed-Timing Domains
[in DAC-01]
{tibi,nowick}@cs.columbia.edu
Introduction
Key Trend in VLSI systems: systems-on-a-chip (SoC)
Two fundamental challenges:
mixed-timing domains
long interconnect delays
Desirable Features:
arbitrarily robust
low-latency, high-throughput
modularity, scalability
Few satisfactory solutions to date….
Timing Issues in SoC Design
sync or Domain #1
async
Domain #1
long long
inter- inter-
connect connect
Domain #2 sync or
async
Domain #2
Timing Issues in SoC Design (cont.)
Solution: provide interface circuits
(a) single-clock (b) mixed-timing domains
sync or Domain #1
Domain #1 async
long long
inter- inter-
connect connect
sync or
Domain #2 async
Domain #2
Two Contributions:
Mixed-Timing FIFO’s
Mixed-Timing Relay Stations
Contribution #1: Mixed-Timing FIFO’s
Addresses issue of interfacing mixed-timing domains
Features: token ring architecture
circular array of identical cells
shared buses: data + control
data: “immobile” once enqueued
distributed control: allows concurrent put/get operations
• Async-Sync Interfaces
FIFO
Relay Station
• Results
• Conclusions
Mixed-Clock FIFO: Block Level
Initiates put operations
InitiatesIndicates
get operations
data items validity
Indicates
Bus forwhen (always
dataFIFO
items full 1 in this design)
Indicates when FIFO empty
full req_get
Mixed-Clock
req_put valid_get
synchronous synchronous
FIFO
empty
put inteface data_put data_get get interface
CLK_put CLK_get
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
Mixed-Clock FIFO: Steady-State Simulation
Passes the put token
TAIL
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
Mixed-Clock FIFO: Steady-State Simulation
TAIL
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
Get Operation
Mixed-Clock FIFO: Steady-State Simulation
TAIL
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
SteadyPuts
Steady state operation: state operation:
and Gets “reasonably spaced”
Zero synchronization
Zero probability overheadfailure
of synchronization
Mixed-Clock FIFO: Steady-State Simulation
TAIL TAIL TAIL
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
Mixed-Clock FIFO: Full Scenario
Put interface stalled FIFO FULL
TAIL
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
Mixed-Clock FIFO: Full Scenario
TAIL
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
Mixed-Clock FIFO: Full Scenario
FIFO NOT FULL
TAIL
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
Mixed-Clock FIFO: Full Scenario
TAIL
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
HEAD
Mixed-Clock FIFO: Cell Implementation
Enables a put
Validity bitoperation Data item in
in Put Part
Synchronous reusable
CLK_put en_put
en_put req_put
req_put data_put
data_put
ptok_out
ptok_out ptok_in
ptok_in
En
Data
StatusValidity
Bits:
Controller
Cell FULL f_i
f_i REG
SR
Cell EMPTY e_ie_i
En
En
gtok_out
gtok_out gtok_in
gtok_in
CLK_get en_get
en_get valid
valid data_get
data_get
reusable
Synchronous Get Part
Enables a get operation Data item out
Validity bit out
Mixed-Clock FIFO: Architecture
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
Synchronization Issues
Challenge: interfaces are highly-concurrent
Global “FIFO state”: controlled by 2 different clocks
CLK_get empty
en_get
CLK_get
CLK_get
CLK_get
req_get
Detects “true empty” (0 empty cells)
Reconfigure whenever active
get interface
Mixed-Clock FIFO: Architecture
full
Full Detector
req_put Put
Controller
data_put
CLK_put
CLK_get
data_get
req_get
Controller
Get
valid_get
empty Empty Detector
Put/Get Controllers
en_get
req_get
full en_put
req_put empty valid_get
valid
• Async-Sync Interfaces
FIFO
Relay Station
• Results
• Conclusions
Relay Stations: Overview
Proposed by Carloni et al. (ICCAD’99)
System 2
RS RS RS RS
CLK
Data Packet = “stop” control = stopIn + stopOut
data item -+apply counter-pressure
Steady State: passstall
- result: datacommunication
on every cycle
validity bit(either valid or invalid)
switch
packetIn packetOut
mux
AR
• In normal operation:
packetIn copied to MR and forwarded on packetOut
Steady state: always pass data Steady state: only pass data
when requested
Data items: both valid & invalid Data items: only valid data
System 2
RS RS MCRS
RS RS
CLK1
CLK CLK2
Mixed-Clock Relay Station derived from the Mixed-Clock FIFO
Change ONLY Put and Get Controllers
stopOut
full Station stopIn
req_get
Mixed-Clock
Mixed-Clock
valid_put
req_put valid_get
valid_get
FIFO
data_put
data_put data_get
data_get
CLK1
CLK_put CLK2
CLK_get
Mixed-Clock Relay Station: Implementation
Mixed-Clock Relay Station vs. Mixed-Clock FIFO
Identical:
- FIFO cells
- Full/Empty detectors (...or can simplify)
Only modify: Put & Get Controllers
to cells valid
• Async-Sync Interfaces
FIFO
Relay Station
• Results
• Conclusions
Async-Sync FIFO: Block Level
full req_get put_req req_get
Mixed-Clock
Async-Sync
req_put valid_get valid_get
put_ack
FIFO
FIFO
empty empty
data_put data_get put_data data_get
CLK_put CLK_get CLK_get
put_ack
put_req
put_data
valid_get
empty Empty Detector
we C
+ OPT reusable
e_i we1
from async
new
DV REG FIFO (Async00)
f_i
En
gtok_in
gtok_out
Micropipeline
System 1
System 2
(async)
(sync)
ARS ARS ASRS RS
optional
CLK2
Outline
• Mixed-Clock Interfaces
FIFO
Relay Station
• Async-Sync Interfaces
FIFO
Relay Station
• Results
• Conclusions
Results
Each circuit implemented:
using both academic and industry tools
MINIMALIST: Burst-Mode controllers [Nowick et al. ‘99]
PETRIFY: Petri-Net controllers [Cortadella et al. ‘97]
Experiments:
various FIFO capacities (4/8/16 cells)
various data widths (8/16 bits)
Results: Latency
Experimental Setup:
- 8-bit data items
- various FIFO capacities (4, 8, 16)