JK Flip Flop

Presented by

Dr. J. Nelson Raja

Assistant Professor
Department of Computer Application
Arul Anandar College ,Karumathur
Madurai
 JK Flip-Flop
 J-Jack K- Kilby (Jack Kilby inventor of Integrated Circuits in
1958. JK flip flop is constructed by using four NAND Gate. JK
flip flop contains a Clock and two inputs J (Set) and K (Reset)
similar to RS flip flop.
 The Q output is connected back to the input of the lower AND
gate. The Q output is connected back to the input of the upper
AND gate.
fcrd
1. When J=K=0, CP=1 then the clock pulse has no effect on the
output and output of the flip flop is same as its previous value ie
No Change in output.

2. When J=0, K=1, CP=1 then the output at the NAND gate
corresponding to J becomes 0 the condition will Reset the flip
flop.

3. When J=1, =K=0, CP=1, the output at the NAND gate

corresponding to K becomes 0, the condition will set the flip flop.

4. When J=K=1, CP=1, the output at the NAND gate corresponding

to K becomes 0, so the flip flop will be in Toggle.
 The Master-Slave JK Flip-flop
 The Master-Slave Flip-Flop is basically two gated SR flip-flops
connected together in a series configuration with the slave having
an inverted clock pulse.

 The Master is positive-level-triggered and the Slave is negative-

level-triggered. Therefore, the Master responds to its J and K
inputs before the slave.

 The outputs from Q and Q from the “Slave” flip-flop are fed back
to the inputs of the “Master” with the outputs of the “Master” flip
flop are connected to the two inputs of the “Slave” flip flop.
 The Master-Slave JK Flip-flop
 Firstly the master flip flop is positive level triggered and
the slave flip flop is negative level triggered, so the
master responds before the slave. If J=0 and K=1, the
high Q' output of the master goes to the K input of the
slave and the clock forces the slave to reset, thus the
slave copies the master.
Master-Slave JK Flip-flop
Master-Slave JK Flip-flop Truth Table