Counter Circuits and

Applications
Group 6
彭柏源 袁鋒 陳康本
 Overview
Analysis of Sequential Circuits.
Ripple Counters.
Design of Divide-by-N Counters.
Ripple Counter ICs.
Applications.
System Design Applications.
Seven-Segment LED Display Decoders.
Synchronous Counters.
Synchronous Up/Down-Counter ICs.
Applications.
Analysis of Sequential Circuits
Using Timing Diagrams to analyze.
 Ripple Counters
J-K flip-flops are in the toggle mode.
Output Q is cascaded to the next clock input.
 Ripple Counters(cont’d)
Ideal Timing Diagram.
 Ripple Counters(cont’d)
Ripple: the input clock trigger isn’t connected
to each flip-flop directly but propagate thru all
the flip-flops. Non-ideal Timing Diagram:
 Ripple Counters(cont’d)
Down counter:
 Design of Divide-by-N
Counters
An example of MOD-5 counter.
 Design of Divide-by-N
Counters (cont’d)
Glitch effect: NAND propagation time 15ns &
Flip-flop Reseting time 30ns (For 74LS76 and
7400).
 Design of Divide-by-N
Counters (cont’d)
MOD-5 counter which counts in the sequence
6-7-8-9-10-6-7-8-9-10-,etc.
 Ripple Counter ICs - 7493
7493: a divide-by-2 and a divide-by-8
MR1,MR2 can be utilized to do MOD-N.
 Ripple Counter ICs – 7493
(cont’d)
External connection as a MOD-16 counter.
 Ripple Counter ICs – 7493
(cont’d)
External connection as a MOD-12 counter.
 Ripple Counter ICs – 7490
7490: a divide-by-2 and a divide-by-5.
1
0 1
0 1
0
 Ripple Counter ICs - 7492
7492: a divide-by-2 and a divide-by-6.

1
0 0
1 01
System Design Application –
A 3-digit decimal counter (000 – 999)
When the count changes from (1001) to
(0000), the 23 output line goes from HIGH to
LOW and trigger the next counter.
Seven-Segment LED Display
Decoders
7447: the most popular common-anode deco
der. It has a lamp test (LT) input for testing
all segments, and it also has ripple blanking
input and output (RBI,RBO).
 Synchronous Counters
Synchronous counters eliminate the
propagation delay problem because all the
clock inputs (cp) are tied to a common clock.
Synchronous Counters(cont’d)
A MOD-6 synchronous binary up-counter.
 Synchronous Up/Down-
Counter ICs
MR(Master
PL(Parallel
Two
When separate Reset):
TCDU(normally
Load) &an
clock D active-HIGH
inputs:
HIGH)
0~D3: becomes
place Reset
CpU forany forit up
counting
LOW,
binary is
resetting
used
valueCto
and on the
for
D Q outputs
indicate
~D that
counting
, and thetominimum
down.
drive zero.
maximum
the
One count
count
PLclock
line isis
LOW.
must
pD 0 3
reached and the
be held HIGH whilecount is about
counting to the
with recycle
other. to
zero(carry
the maximum(borrow
condition). condition).
It can be usedIt can
as the
be
next stage
used as theofnexta multistage
stage of acounter.
multistage
counter.
Applications of Synchronous
Counter ICs
A divide-by-200 using synchronous counters.

Parallel Load Value 200

Borrow Condition