UNIT-II MOS TRANSISTOR

THEORY
Prepared by
M.Rajmohan
AP/ECE
HITS
MOS Transistor - Symbols

pMOS Transistor nMOS Transistor

 Operation – nMOS Transistor

 Accumulation Mode - If Vgs < 0, then an electric field is

established across the substrate.
 Depletion Mode -If 0<Vgs< Vtn, the region under gate will
be depleted of charges.
 Inversion Mode – If Vgs > Vtn, the region below the gate will
be inverted.
Operation – nMOS Transistor
Operation – nMOS Transistor

V =0
Operation – nMOS Transistor
Operation – nMOS Transistor
 MOS Capacitor
• Gate and body form MOS capacitor
• Operating modes Vg < 0
polysilicon gate
silicon dioxide insulator

– Accumulation +
- p-type body

– Depletion (a)

– Inversion
0 < V g < Vt
depletion region
+
-

(b)

V g > Vt
Example with an NMOS +
inversion region
depletion region
capacitor -

(c)
 Terminal Voltages
V
• Mode of operation depends on Vg, Vd, Vs g

+
– Vgs = Vg – Vs Vgs
+
Vgd
– Vgd = Vg – Vd - -
Vs Vd
– Vds = Vd – Vs = Vgs - Vgd -
Vds +

• Source and drain are symmetric diffusion terminals

– However, Vds  0
• NMOS body is grounded. First assume source may be grounded or may be
at a voltage above ground.
• Three regions of operation
– Cutoff
– Linear
– Saturation
 nMOS Cutoff
• Let us assume Vs = Vb
• No channel, if Vgs = 0
• Ids = 0 Vgs = 0
+ g +
Vgd

- -
s d

n+ n+

p-type body
b
 NMOS Linear
• Channel forms if Vgs > Vt
Vgs > Vt
• No Currernt if Vds = 0 + g +
Vgd = Vgs

- -
s d
n+ n+ Vds = 0

p-type body
b

• Linear Region:
Vgs > Vt
• If Vds > 0, Current flows + g +
Vgs > Vgd > Vt

- -
from d to s ( e- from s to d) s d
Ids

• Ids increases linearly n+ n+

0 < Vds < Vgs-Vt
with Vds if Vds > Vgs – Vt. p-type body

• Similar to linear resistor b

 NMOS Saturation
• Channel pinches off if Vds > Vgs – Vt.
• Ids “independent” of Vds, i.e., current saturates
• Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b
 The Threshold Voltage
The value of VGS where strong inversion occurs is called the Threshold Voltage, VT ,
and has several components:
•The flat-band voltage, VFB , is the built-in voltage offset across the MOS structure
and depends on fixed charge and implanted impurities charge on the oxide-
silicon interface
•VB represents the voltage drop across the depletion layer at inversion and
equals to minus twice the Fermi potential ~(0.6V)
•Vox represents the potential drop
across the gate oxide

VT  VFB  VB  Vox
The Threshold Voltage
Where:
F is the Fermi potential ( ~ -0.3V for p-type
substrates
Cox is the gate oxide capacitance
VSB is the substrate bias voltage
VT0 is VT at VSB = 0

Note:
VT is positive for NMOS transistors and
negative for PMOS
 Body effect
• The most general form of the
threshold voltage is: VT=GC-
2F-Qox/Cox-QB/Cox
VT  VT 0      2 F  VSB  2 F 
• VT=VT0-(QB-QB0)/Cox

• (QB-QB0)/Cox=((2qNASi)-1/2)
/Cox*((|-2F+VSB|)-1/2-(|2F|)-1/2)

• This becomes the most general 2qN A Si


expression of the threshold Cox
voltage with the parameter
gamma being:
 MOS equations
Basic DC equations
Contd..
CMOS inverter DC characteristics
Contd..
 DC Characteristics of a CMOS Inveter
• The DC transfer characteristic curve
is determined by plotting the common
points of Vgs intersection after taking
the absolute value of the p-device IV
curves, reflecting them about the x-
axis and superimposing them on the
n-device IV curves.
• We basically solve for Vin(n-type) =
Vin(p-type) and Ids(n-type)=Ids(p-type)
• The desired switching point must be
designed to be 50 % of magnitude of
the supply voltage i.e. VDD/2.
• Analysis of the superimposed n-type
and p-type IV curves results in five
regions in which the inverter operates.
• Region A occurs when 0 leqVin leq
Vt(n-type).
– The n-device is in cut-off (Idsn =0).
– p-device is in linear region,
– Idsn = 0 therefore -Idsp = 0
– Vdsp = Vout – VDD, but Vdsp =0 leading
to an output of Vout = VDD.
• Region B occurs when the condition
Vtn leq Vin le VDD/2 is met.
– Here p-device is in its non-saturated
region Vds neq 0.
– n-device is in saturation
• Saturation current Idsn is obtained by
setting Vgs = Vin resulting in the
equation:
n
I dsn  Vun  Vtn 2
2
CMOS Inverter DC Characteristics
 CMOS Inverter Transfer Characteristics

• In region B Idsp is governed by • Region D is defined by the inequality

VDD
voltages Vgs and Vds described by:  Vin  VDD  Vtp
2
V gs  Vin  VDD  and Vds  Vout  VDD  • p-device is in saturation while n-
  V  VDD  
I dsp    p Vin  VDD  Vtp Vout  VDD  out
2


device is in its non-saturation region.
  2 
p
Recall that :  I dsn  I dsp


n
Vin  Vtn 2   p Vin  VDD  Vtp Vout  VDD   Vout  VDD 
 2
 I dsp   Vin  VDD  Vtp 2 ; Vin  Vtp  VDD
2  2


2
• Region C has that both n- and p- AND
devices are in saturation.   Vout  
2

• Saturation currents for the two I dsn   n Vin  Vtn Vout    ; Vin  Vtn
  2  
devices are: • Equating the drain currents allows us
p
I dsp   Vin  VDD  Vtp 2 ; Vin  Vtp  VDD to solve for Vout. (See supplemental
2 notes for algebraic manipulations).
AND

I dsn  n Vin  Vtn  ; Vin  Vtn
2

2
 CMOS Inverter Static Charateristics

• In Region E the input condition • nMOS & pMOS Operating points

satisfies: Vout =Vin-Vtp
A

Vin  VDD  Vtp

VD B
D
Vout =Vin-Vtn

Output Voltage
• The p-type device is in cut-off: Idsp=0 Both in sat
• The n-type device is in linear mode C nMOS in sat
• Vgsp = Vin –VDD and this is a more pMOS in sat
positive value compared to Vtp.
• Vout = 0
D E
0
Vtp Vtn VDD/2 VDD+Vt VD
p D
 Transmission Gates
• Transmission gates pass both 0 and 1 well

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb
 Tristate Inverter
• Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
EN
Y
EN
 Power Dissipation

 Power dissipation in CMOS circuits comes from two components:

 Static Dissipation
 Subtreshold conduction
 Tunneling current
 Leakage through reverse biased diodes

 Dynamic Dissipation
 Charging and discharging (switching) of the load capacitance
 “Short-Circuit” current while both pMOS and nMOS networks are partially
ON
 Static Dissipation
Pstatic  VDD  I leakage
• OFF transistors still conduct a small amount of current :
– Sub threshold current
– Current through reverse biased diodes
– gate tunneling current