Lecture 11

Memory Design

Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998

ECE C03 Lecture 11 1

 Outline
• Random Access Memories (RAMS)
• Static RAMs
• Dynamic RAMS
• Memory Organizations
• Read-Only Memories (ROMS)
• READING: Katz 7.6, 4.2.5

ECE C03 Lecture 11 2

 Memory
• Need method for storing large amounts of data
– Computer programs, data, pictures, etc.
Address Data
000000 00111110 64x8 RAM
000001 01101011
000010 01011101 A3 D7
000011 01100011 A2 D6
000100 00111110 A1 D5
000101 00000000 A0 D4
000110 11111111 D3
000111 01010101 D2
001000 10101010
D1
001001 00100001
001010 11011010 Write D0

• RAM: Random Access Memory, Read/Write

• ROM: Read-only Memory
ECE C03 Lecture 11 3
 8x4 RAM
Address Data
000

001

010

011

100

101

110

111

A2
A1
A0 ECE C03 Lecture 11 4
Out3 Out2 Out1 Out0
 8x4 RAM
In3 In2 In1 In0
Write
000

001

010

3:8 011
Decoder
100

101
Enable
110

111
S2 S1 S0
A2
A1
ECE C03 Lecture 11 5
A0 Out3 Out2 Out1 Out0
 RAM Cell
• Requirements:
– Store one bit of data
– Change data based on input when row is selected

Input S
Q
Row Select R

ECE C03 Lecture 11 6

 Static Random Access Memories
Transistor efficient methods for implementing storage elements

Small RAM: 256 words by 4-bit

Large RAM: 4 million words by 1-bit

We will discuss a 1024 x 4 organization

Data Data j
j
Word Enable
i

Words = Rows Static RAM Cell

Static RAM Cell Static RAM Cell

Columns = Bits
ECE C03 (Double
Lecture 11 Rail Encoded) 7
 Static RAM Organization

1024 x 4 SRAM
CS
Chip Select Line (active lo) WE
A9
Write Enable Line (active lo) A8
A7 IO3
A6 IO2
10 Address Lines A5 IO1
A4 IO0
4 Bidirectional Data Lines A3
A2
A1
A0

ECE C03 Lecture 11 8

 RAM Organization
Long thin layouts are not the best organization for a RAM
A9
Address
Buffers
A8
Storage
Storage Matrix
Array
Some Addr A7 64 x 64
bits select Square
row A6 Array
A5 64 x 16 64 x 16 64 x 16 64 x 16
Row
A4 Decoders

A3 Address
Buffers
Some Addr A2
Amplifers &
Sense Amplifiers
bits select A1 Mux/Demux
within row Column
A0 Decoders

CS
Data Buffers
WE

I/O0 C03 Lecture

ECE I/O1 11 I/O2 I/O3 9
 RAM Timing
WE

CS
Simplified Read Timing

Address Valid Address

Ac cess Time

Data Out Data Out

WE

CS
Simplified Write Timing
Memory Cy cle T ime
Address Valid Address

Data In Input Data

ECE C03 Lecture 11 10

 Dynamic Random Access Memories
1 Transistor (+ capacitor) memory element
Word Line Read: Assert Word Line, Sense Bit Line

Write: Drive Bit Line, Assert Word Line

Destructive Read-Out

Need for Refresh Cycles: storage decay in ms

Bit Line
Internal circuits read word and write back

ECE C03 Lecture 11 11

 DRAM Organization
Long rows to simplify refresh

Two new signals: RAS, CAS Row

Storage Matrix
Decoders 64 x 64
Row Address Strobe

Column Address Strobe

replace Chip Select

Row Address
Column Address &
Control Signals
A11
. . . Column Latches,
Multiplexers/Demultiplexers
A0 Control
RAS Logic
CAS
WE
DOUT DIN

ECE C03 Lecture 11 12

 RAM Addressing
Even to read 1 bit, an entire 64-bit row is read!

Separate addressing into two cycles: Row Address, Column Address

Saves on package pins, speeds RAM access for sequential bits!

Address Row Address Col Address

RAS
Read Cycle
CAS

Dout Valid
Read Row
Row Address Latched
Read Bit Within Row Tri-state
Column Address Latched Outputs

ECE C03 Lecture 11 13

 RAM Write Timing
Address Row Address Col Address

RAS

(1) Latch Row Address CAS

Read Row
WE

(2) WE low
Din Valid

(3) CAS low: replace data bit

(4) RAS high: write back the modified row

(5) CAS high to complete the memory cycle

ECE C03 Lecture 11 14
 DRAM Refresh
Refresh Frequency:
4096 word RAM -- refresh each word once every 4 ms

Assume 120ns memory access cycle

This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)!

But RAM is really organized into 64 rows

This is one refresh cycle every 62.5 µs (1 in 500 DRAM accesses)

Large capacity DRAMs have 256 rows, refresh once every 16 µs

RAS-only Refresh (RAS cycling, no CAS cycling)

External controller remembers last refreshed row

Some memory chips maintain refresh row pointer

CAS before RAS refresh: if CAS goes low before RAS, then refresh
ECE C03 Lecture 11 15
 Variations of DRAMs
Page Mode DRAM:
read/write bit within last accessed row without RAS cycle

RAS, CAS, CAS, . . ., CAS, RAS, CAS, ...

New column address for each CAS cycle

Static Column DRAM:

like page mode, except address bit changes signal new cycles
rather than CAS cycling

on writes, deselect chip or CAS while address lines are changing

Nibble Mode DRAM:

like page mode, except that CAS cycling implies next column
address in sequence -- no need to specify column address after
first CAS

Works for 4 bits at a time (hence "nibble")

RAS, CAS, CAS, CAS, CAS, RAS, CAS, CAS, CAS, CAS, . . .
ECE C03 Lecture 11 16
 RAM Expansion
• Implement a big RAM from multiple small RAMS
Address D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0000000

0010000

0100000

0110000

1000000

1010000

1100000

1110000
ECE C03 Lecture 11 17
 RAM Expansion (cont)
• Build a 16x16 RAM from 16x4 RAMs

16x4 RAM 16x4 RAM 16x4 RAM 16x4 RAM

A3 Din A3 Din A3 Din A3 Din
A2 A2 A2 A2
A1 Dout A1 Dout A1 Dout A1 Dout
A0 A0 A0 A0
Write Write Write Write

ECE C03 Lecture 11 18

 RAM Expansion (cont)
• Build a 32x16 RAM from 16x4 RAMs

16x4 RAM 16x4 RAM 16x4 RAM 16x4 RAM

A3 Din A3 Din A3 Din A3 Din
A2 A2 A2 A2
A1 Dout A1 Dout A1 Dout A1 Dout
A0 A0 A0 A0
Write Write Write Write

16x4 RAM 16x4 RAM 16x4 RAM 16x4 RAM

A3 Din A3 Din A3 Din A3 Din
A2 A2 A2 A2
A1 Dout A1 Dout A1 Dout A1 Dout
A0 A0 A0 A0
Write Write Write Write

ECE C03 Lecture 11 19

 Read-Only Memories
This is another class of memory, which is read only, cannot write.
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"

Width of row is called bit-width or wordsize

Address is input, selected word is output

+5V +5V +5V +5V

n
2 -1

i Word Line 0011

Dec
j Word Line 1010

Bit Lines
0 n-1
Address

InternalECE C03 Lecture 11

Organization 20
 ROMs vs PLAs
Not unlike a PLA Memory array
structure with a
fully decoded Decoder 2n w ord 2n w ords by
AND array! lines m bits

n addres s m output
lines lines

ROM vs. PLA:

ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions

ROM problem: size doubles for each additional input, can't use don't cares

PLA approach advantangeous when

(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions

PAL problem: constrained fan-ins on OR

ECE C03 Lecture 11 planes 21
 Read-Only Memories
2764 EPROM 2764 2764
8K x 8 +
VPP
PGM +
VPP
PGM
A12 A12
A11 A11
2764 A10 O7 A10 O7
A9 O6 A9 O6
VPP A8 O5 A8 O5
A7 O4 A7 O4
PGM A6 O3 A6 O3
A5 O2 A5 O2
A12 A4 O1 A4 O1
A11 A3 O0
A2
A3 O0
A2
A10 O7 A1 A1
A0 A0
A9 O6 CS U3 CS U2
OE OE
A8 O5
A7 O4
A13
A6 /OE
O3 A12:A0
A5 O2 D15:D8
A4 D7:D0
O1 2764 2764
A3 VPP VPP
O0 + PGM + PGM
A2 A12 A12
A11
A11
A1 A10 O7 A10 O7
A9 O6 A9 O6
A0 A8 O5 A8 O5
CS A7 O4 A7 O4
A6 O3 A6 O3
OE A5 O2 A5 O2
A4 O1 A4 O1
A3 O0 A3 O0
A2 A2
A1 A1
A0 A0
CS U1 CS U0
OE OE
16K x 16
Subsystem
ECE C03 Lecture 11 22
 Implementing Logic with ROMs

F0 = A' B' C + A B' C' + A B' C

F1 = A' B' C + A' B C' + A B C

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C'

Addres s A B C F0 F1 F2 F3 Word Contents
0 0 0 0 0 1 0
0 0 1 1 1 1 0
0 1 0 0 1 0 0
ROM 0 1 1 0 0 0 1
8 words ¥by 1 0 0 1 0 1 1
4 bits 1 0 1 1 0 0 0
1 1 0 0 0 0 1
1 1 1 0 1 0 0

A B C F0 F1 F2 F3
addres s outputs
ECE C03 Lecture 11 23
 Summary
• Random Access Memories (RAMS)
• Static RAMs
• Dynamic RAMS
• Memory Organizations
• Read-Only Memories (ROMS)
• NEXT LECTURE: Finite State Machine Design
• READING: Katz 8.1, 8.2, 8.4, 8.5, Dewey 9.1, 9.2

ECE C03 Lecture 11 24