4.

3 Combinational-Circuit Synthesis
1. Approach to Circuit Designs
 According to the descriptions of a circuit logic
function, write the truth table.
 Transform the truth table into logic expression.

 Simplify or transform the logic expression, and

then draw the logic circuit diagram.
2. Circuit Descriptions
 The description is a list of input combinations.
Example: Given a 4-bit input combination
N=N3N2N1N0, this function produces a 1 output
for N=1,2,3,5,7,11,13, and 0 otherwise.
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 4.3 Combinational-Circuit Synthesis

F  N (1,2,3,5,7,11,13)  N 3  N 2  N1  N 0 
3 , N 2 , N1 , N 0

N 3  N 2  N1  N 0  N 3  N 2  N1  N 0  N 3  N 2  N1  N 0 
N 3  N 2  N1  N 0  N 3  N 2  N1  N 0  N 3  N 2  N1  N 0

 The description is a word or sentence, called

“natural” logic expression. Such a description
need to be translated into algebraic expressions.

Examples: (P215-217)

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 4.3 Combinational-Circuit Synthesis
3. Circuit Manipulations
NAND and NOR gates are faster than ANDs
and ORs in most technologies. So, we need
ways to translate descriptions using AND, OR,
and NOT gates into other forms.
 An AND-OR circuit converts into a NAND-NANDs
 We can obtain an equivalent sum-of-products
expression for any logic expression. It may be
realized directly with AND and OR gates. The
inverters required for complemented inputs are
not included.
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4.3 Combinational-Circuit Synthesis
 We may insert a pair of
inverters between AND-
gate output and the
corresponding OR-gate
input in a two-level AND-
OR circuit.

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 4.3 Combinational-Circuit Synthesis
 An OR-AND circuit converts into a NOR-NORs
(See P219)
4. Combinational-Circuit Minimization
 The methods to minimize a combinational circuit
classified two types:
 Algebraic method.

 Karnaugh map method.

Minimization using the algebraic method is

difficult to find terms that can be combined in a
jumble of algebraic symbols.
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 4.3 Combinational-Circuit Synthesis
 Most algebraic methods are based on a
generalization of the combining
theorems, T10 and T10’:
 given product term·y+ given product
term·y = given product term
 (given sum term+y) ·(given sum

term+y ) = given sum term

We can apply this algebraic method
repeatedly to combine minterms
1,3,5,7 of the prime-number detector.
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 4.3 Combinational-Circuit Synthesis

F  N (1,2,3,5,7,11,13)  N 3  N 2  N1  N 0 
3 , N 2 , N1 , N 0

N 3  N 2  N1  N 0  N 3  N 2  N1  N 0  N 3  N 2  N1  N 0 
N 3  N 2  N1  N 0  N 3  N 2  N1  N 0  N 3  N 2  N1  N 0

 N 3  N 2  N 0  N 3  N 2  N1  N 0  N 3  N 2  N 0
 N 3  N 2  N1  N 0  N 3  N 2  N1  N 0

 N3  N0  N3  N 2  N1  N0  N3  N 2  N1  N0  N3  N 2  N1  N0

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 4.3 Combinational-Circuit Synthesis
5. Karnaugh Maps
A Karnaugh Map is a graphical representation
of a logic function’s truth table.
y yz y
y wx
x 0 1 00 01 11 10
Gray 00
0 0 1 0 1 3 2
Code
1 2 3 x
01 4 5 7 6
yz y x
x 00 01 11 10 11 12 13 15 14
w
0 0 1 3 2 8 9 11 10
10
1 4 5 7 6 x
z
z Return Back Next
 4.3 Combinational-Circuit Synthesis
6. Minimizing Sums of Products
Examples.
Simplify the following logic function:
(1) F=∑x,y,z(1,2,5,7)
(2) F  x  y  z  x  y  z  x  y  z  x  y  z  x  y  z
yz yz
x 00 01 11 10 x 00 01 11 10
0 1 1 0 1 1
1 1 1 1 1 1 1

F  y z  x z  x y z F  y  xz
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 4.3 Combinational-Circuit Synthesis
 A set of 2i 1-cells may be combined to
form a product term containing n-i literals.
 In every product term a variable is
complemented if it appears only as 0 in all
of the 1-cells.
 In every product term a variable is

uncomplemented if it appears only as 1 in

all of the 1-cells.
 In every product term a variable dose not

appear if it appears both as 0 and 1 in the

set of 1-cells. Return Back Next
 4.3 Combinational-Circuit Synthesis
 The number of 1s in  A circled rectangular set
the circled rectangular of 1s must include a new
set must be 2i. minterm(not be circled).
yz yz
x 00 01 11 10 wx 00 01 11 10
0 1 1 00
1 1
1 1 1
01 1 1 1
yz
x 00 01 11 10 11 1 1
0 1 1 1 1
10
1 1 1 1
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 4.3 Combinational-Circuit Synthesis
A circled rectangular should be the largest
possible set of 1s.
yz yz
wx 00 01 11 10 wx 00 01 11 10
00 00
1 1 1 1 1
01 1 1 1 01 1 1

11 1 1 11 1 1 1

10 1 10 1 1

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 4.3 Combinational-Circuit Synthesis
 All the product term of 1s must be circled once
at least. yz
x 00 01 11 10
0 1 1
1 1 1

 A minimal sum of a logic function F(x1, …,xn)

is a sum-of-products expression for F such that
no sum-of-products expression for F has fewer
product terms, and any sum-of-products
expression with the same number of product
terms has at least as many literals.
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 4.3 Combinational-Circuit Synthesis
Example
F  x y z  x y z  x y z  x y z  x y z
It isn’t a minimal sum. It can be simplified as
F  y z  x z  x y z
 A logic function P (x1, …,xn) implies a logic
function F (x1, …,xn) if for every input combination
such that P=1, then F=1 also.
Example
Suppose F  z  x  y  z or F  x y  x y
P  x y
Then, P implies F, or F includes P, or F covers
P, or P  F . Return Back Next
 4.3 Combinational-Circuit Synthesis
 A prime implicant of a logic function F(x1, …,xn)
is a normal product term P(x1, …,xn) that implies
F, such that if any variable is removed from P, then
the resulting product term does not imply F.
Example
Suppose F  z  x yz P  x y
Then, P implies F. But if the variable x or y is
removed from P, e.g. if x is removed from P,
P  y 1 F  z  x yz  z  xz  z  x
When P=1, F maybe not 1. So P does not imply
F. The same as y is removed from P. So P is a
prime implicant of F. Return Back Next
 4.3 Combinational-Circuit Synthesis
 Prime-Implicant Theorem: A minimal sum is a
sum of prime implicant which is called complete
sum. yz
wx 00 01 11 10 Prime
00 implicants
1 1
01 1 1

11 1 1
Not a prime
10 1 implicant

Minimal sum F  y  z  x  z  w x  y
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 4.3 Combinational-Circuit Synthesis
 A distinguished 1-cell of a logic function is an
input combination that is covered by only one
prime implicant.  An essential prime
Distinguished implicant of a logic
yz 1-cell
function is a prime
wx 00 01 11 10
implicant that covers
00
1 1 one or more
01 1 1 1 distinguished 1-cell.
Not an essential
11 1 1 1 prime implicant

10 1 F  x  y  y  z  w x  y
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 4.3 Combinational-Circuit Synthesis
 Reduce map is yz F  w  y  y  z  x  y  w  x  y
obtained by removing wx 00 01 11 10
the essential prime 00
implicant and the 1-
cells they cover. 01
yz 1
wx 11
00 01 11 10
00
1 1 10
01 1 1  Given two prime implicants
P and Q in a reduced map, P
11 1 1 1 is said to eclipse Q if P covers
1 1 at least all the 1-cells covered
10
by Q. Return Back Next
 4.3 Combinational-Circuit Synthesis
yz F  w x  z  w x  y  w y  z  w x  y
wx 00 01 11 10
00 yz
wx 00 01 11 10
01 1 1 00

11 1 1 01

10 1 1 1 1
11
 The two 1-cells in the 10
reduced map are covered
only by x.y.z is a secondary F  w  x  y  w  x  z  w  x  y
essential prime implicant.
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 4.3 Combinational-Circuit Synthesis
7. Simplifying Products of Sums
 Using the principle of yz
duality, we can minimize wx 00 01 11 10
product-of-sums 00
expressions by looking at 0 0 0 0
the 0s on a Karnaugh map. 01 0 0
Each 0 on the map
corresponds to a maxterm 11 0 0
in the canonical product of
the logic function. Writing 10 0 0
sum terms correspond-ing
to circled sets of 0s, in F  (w  y)  ( x  y)  (w  x  z)
order to find a minimal
product. Return Back Next
 4.3 Combinational-Circuit Synthesis
7. Simplifying Products of Sums
 Another way: The first yz
wx 00 01 11 10
step is to complement F 00
1 1 1 1
to obtain F, next find a
minimal sum for F, finally, 01 1 1
complement the result 11 1 1
using the generalized
10 1 1
DeMorgan’s theorem,
F=F. F  w y  x  y  w x  z
F  F  w  y  x  y  w  x  z  ( w  y)  ( x  y)  (w  x  z )
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 4.3 Combinational-Circuit Synthesis
8. “Don’t-Care” Input Combinations
 Don’t-cares: Sometimes the specification of a
combinational circuit is such that its output
doesn’t matter for certain input combinations,
called don’t-cares.
 Example: Prime BCD-digit detector.
yz
F  w, x , y , z (1,2,3,5,7)
wx 00 01 11 10
00 1 1 1
01 1 1  d (10,11,12,13,14,15)
11 d d d d F  w z  x  y
10 d d
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 4.3 Combinational-Circuit Synthesis
9. Multiple-Output Minimization
 Most practical combinational logic circuits
require more than one output.
 Example

F  x , y , z (3,6,7) G  x , y , z (0,1,3)
yz yz
x 00 01 11 10 x 00 01 11 10
0 1 0 1 1 1
1 1 1 1

F  x y  y z G  x y  x z
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 4.3 Combinational-Circuit Synthesis
x x y
F  x y  y z
y yz
z
y x y
x G  x y  xz
x z

We can also find a pair of sum-of-products

expressions that share a product term, such
that the resulting circuit has one fewer gate
than our original design.
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 4.3 Combinational-Circuit Synthesis
yz yz
x 00 01 11 10 x 00 01 11 10
0 1 0 1 1 1
1 1 1 1
F  x y  x y z G  x y  x y z
x x y
F  x y  x y z
y
z
x x yz G  x y  x y z
y
x y Return Back