Digital Front End Transmitter Side

Clock Manager
Clk_out1
Clk Clk
Clk_out2 s_clk
rst

data_v Fir_Interpolator Digital_Mixer(IF

conversion) SPI_ADC_interfacing
data_out_I_trun(15:0) LDA
s_clk
Clk_out1
data_out_Q_trun(15:0) rdy_1
mosi
rst Clk_out1
Mul_trans(15:0)
dv_out
data_v ss
rdy rst
 Fir_Interpolator
Fir Interpolator core I
clk
rfd
sclr Controller
data_valid
nd
rdy rdy
16 I ce
round Trunc
30 I 30 I data_out_I_trun(15:0)
15 I

rst Fir Interpolator core Q

sclr rfd

16 I nd data_valid

ce rdy
round Trunc
30 Q 30 Q 15 Qdata_out_Q_trun(15:0)
 Digital_Mixer(IF conversion)
clk rdy_1 rdy_1
rfd
22
Phase_out

cosine 6
Controller
sine 6
rst

data_out_I_trun(15:0)
16 22
Mul_trans
round Trunc
22 22 16
data_out_Q_trun(15:0)
16 22
 SPI_ADC_interfacing

s_clk LDA

rst mosi
Mul_trans 16 Register
ss
 Fir interpolator State Machine
data_v=0 rst=1
data_v=1 rst=0

Initial Count_initial_delay<8
Ce=0; rst=1
Nd=0;
Sclr=1;
rst=1 Start
Ce=0;
Nd=0;
Sclr=1;

Process
Ce=1;
Nd=1;
Sclr=0;

Count_initial_delay==8
Digital_Mixer(IF conversion) Statemacine

dv_out_fir =0 rst=1

Initial
Ce=0;
Sclr=1; dv_out_fir =1 rst=0
Start=1;

rst=1

Start
Ce=1;
Nd=1;
Sclr=0;