Introduction To Digital Electronics: Microelectronic Circuit Design

Chapter 6
Introduction to Digital Electronics
Microelectronic Circuit Design

Richard C. Jaeger
Travis N. Blalock
Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 1

9/25/03 McGraw-Hill
Ideal Logic Gates
• Binary logic gates are the most common style of
digital logic
• The output will consist of either a 0 (low) or a 1 (high)
• The most basic digital building block is the inverter

9/25/03 McGraw-Hill
The Ideal Inverter
The ideal inverter has the following voltage transfer characteristic

(VTC) and is described by the following symbol
V+ and V- are the supply rails, and VH and VL describe

the high and low logic levels at the output
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Logic Level Definitions
An inverter operating with power supplies at V+ and

0 V can be implemented using a switch with a
resistive load
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Logic Voltage Level Definitions
• VL – The nominal voltage corresponding to a low-logic
state at the input of a logic gate for vi = VH
• VH – The nominal voltage corresponding to a high-logic
state at the output of a logic gate for vi = VL
• VIL – The maximum input voltage that will be recognized
as a low input logic level
• VIH – The maximum input voltage that will be recognized
as a high input logic level
• VOH – The output voltage corresponding to an input
voltage of VIL
• VOL – The output voltage corresponding to an input
voltage of VIH
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Logic Voltage Level Definitions (cont.)
Note that for the VTC of the nonideal inverter, there is now an
undefined logic state
9/25/03 McGraw-Hill
Noise Margins
• Noise margins represent “safety margins” that

prevent the circuit from producing erroneous
outputs in the presence of noisy inputs
• Noise margins are defined for low and high input
levels using the following equations:
NML = VIL – VOL
NMH = VOH – VIH

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Noise Margins (cont.)
• Graphical representation of
where noise margins are
defined

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NMOS Logic Design
• MOS transistors (both PMOS and NMOS) can be

combined with resistive loads to create single
channel logic gates
• The circuit designer is limited to altering circuit

topology and width-to-length, or W/L, ratio since
the other factors are dependent upon processing
parameters

9/25/03 McGraw-Hill
NMOS Inverter with a Resistive Load
• The resistor R is used

to “pull” the output
high
• MS is the switching
transistor
• The size of R and the
W/L ratio of MS are
the design factors that
need to be chosen

9/25/03 McGraw-Hill
Load Line Visualization
• The following
illustrates the
operation of the
NMOS output (vDS)
characteristics where
the following
equation describes
the load line
vDS  VDD  iD R
9/25/03 McGraw-Hill
NMOS with Resistive Load Design
Example
• Design a NMOS resistive load inverter for
– VDD = 3.3 V
– P = 0.1 mW when VL = 0.2 V (chosen to be between
25% and 50% of VTN to ensure that Ms is in cutoff
when the input is low and an adequate noise margin)
– Kn = 60 μA/V2
– VTN = 0.75 V
• Find the value of the load resistor R and the W/L
ratio of the switching transistor MS

9/25/03 McGraw-Hill
Example continued
• First the value of the current through the resistor

must be determined by using the following:
P 0.1mW
I DD    30.3A
VDD 3.3V
• The value of the resistor can now be found by the
following which assumes that the transistor is on
or the output is low:
VDD  VL 3.3V  0.2V
R   102k
I DD 30.3A

9/25/03 McGraw-Hill
Example Continued
• For vI = VL = 0.2V, the transistor’s vGS will be less

than the threshold voltage, therefore it will be
operating in the triode region. Using the linear
equation for a MOSFET, the W/L ratio can be
found:
W   VL 
I D  K   VH  VTN  VL
'
n
 L S  2 
 
6  W  
30.3A  60  10    3.3  0.75 
0 .2 
 0 .2
 L S  2 
 W  1.03 1
   
 L S 1 1
9/25/03 McGraw-Hill
On-Resistance of MS
• The NMOS resistive load

inverter can be thought of
as a resistive divider
when the output is low,
described by the
following expression:
Ron
VL  VDD
Ron  R
9/25/03 McGraw-Hill
On-Resistance of MS (cont.)
When the NMOS resistive load inverter’s output is

low, the On-Resistance of the NMOS can be
calculated with the following expression:
vDS 1
Ron  
iD  W  vDS 
K   vGS  VTN 
'
n 
 L  2 
Note that Ron should be kept small compared to R to
ensure that VL remains low. Also, notice that its
value is nonlinear since it depends on vDS
9/25/03 McGraw-Hill
Noise Margin Analysis
• The following equations can be used to determine

the various parameters needed to determine the
noise margin of NMOS resistive load inverters
1
VIL  VTN 
Kn R
1
VOH  VDD 
2K n R
1 V
VIH  VTN   1.63 DD
Kn R Kn R
2VDD
VOL 
3K n R
9/25/03 McGraw-Hill
Noise Margin Analysis
To find VIL & VOH

• Assume saturation region operation
(VDS = vO=VOH > vGS-VTN= VIL-VTN)
• Substitute iD in load-line expression
• Set dvO/dvI = 0 and solve for vI=vIL
To find VIH and VOL

• Assume triode –region operation
• Repeat above steps

9/25/03 McGraw-Hill
Load Resistor Problems
• For completely
integrated circuits, R
must be implemented on
chip using the shown
structure
• Using the given
L
R equation, it can be seen
tW
that resistors take up a
L Rt  95k  110 cm  9500 large area of silicon as
4
  
W  0.001  cm 1 in an example 95kΩ
resistor
9/25/03 McGraw-Hill
Practice
• P6.46: Design a resistive load inverter to operate from a
2.5V supply with a power dissipation of 50 µW. Assume
VT=0.60V.
• P6.47: Find VH, VL and the power dissipation for vi=VL for
the inverters shown.

9/25/03 McGraw-Hill
Reference Design
Use this design as the reference inverter for complex

logic gate problems.

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NOR Gates
For resistive-load, replace load transistor ML with load resistance
Two-input NOR gate Simplified switch model for

the NOR gate with A on
9/25/03 McGraw-Hill
NAND Gates
Two-input NAND gate

(left)
Simplified switch model

for the NOR gate with A
and B on (right)

9/25/03 McGraw-Hill
NAND Gate Device Size Selection
• The NAND switching transistors can be sized based on the

reference inverter
• To keep the low voltage level to be comparable to the
inverter, the desired RON of MA and MB must be 0.5RON of
MS,Inverter
• This can be accomplished by approximately doubling the
(W/L)A and (W/L)B
• The sizes can also be chosen by using the design value of
VL and using the following equation:
W  W 
iD  K n'    vGS  VTN  0.5vDS  vDS  K n'    vGS  VTN  vDS
 L S  L S
9/25/03 McGraw-Hill
NAND Gate Device Size Selection
(continued)
• Two sources of error that arise are the facts that
VSB and VGS of the two transistors do not equal.
These factors should be considered for proper gate
design
• The technique used to calculate the size of the load

transistor for the depletion-mode load inverter is
the exact same as for this NAND gate

9/25/03 McGraw-Hill
Complex NMOS Logic Design
An advantage of NMOS technology is that it is simple to design

complex logic functions based on the NOR and NAND gates
The circuit in the

figure has the logic
function:
Y = A + BC + BD

9/25/03 McGraw-Hill
Complex Logic Gate Transistor Sizing
• There are two ways to find the W/L ratios of the

switching transistors
1) Using the worst case (longest) path and choosing the

W/L ratio such that the RON of the multiple legs match
similar to the technique used to find the W/L ratios in
the NAND Gate
2) Partitioning the circuit into series sub-networks, and

make the equivalent on-resistances equal

9/25/03 McGraw-Hill
Complex Logic Gate Transistor Sizing
The figure on the left

shows the worst case
technique to find the
sizes where
(W/L)S=2.06 is the
reference inverter ratio
for this technology and
the longest path is 3
transistors are in series
The figure on the right

shows the partitioning
technique to find the
sizes which gives two
4.12/1 ratios in series
which is 2(2.06/1)

9/25/03 McGraw-Hill
Example 6.10

9/25/03 McGraw-Hill
Prob. 6.96
(a) What is the logic function?

(b) Find W/L ratios if design
is based on fig. 6.32(d)
(W/L)L=1/2.15
(W/L)S=2.06/1

9/25/03 McGraw-Hill
Prob. 6.98
a) Find logic function

b) Find (W/L)’s if the gate is to
dissipate 3 times the power of
reference design in fig. 6.32(d)
(W/L)L=1/2.15
(W/L)S=2.06/1

9/25/03 McGraw-Hill
Recommended Practice Problems
Secs 6.11-6.14
• 92, 93, 95, 97, 98,
99,102,103,110,116,119,122,123,124,125,128,
130,136,137
• Solutions can be found at:
~mtoledo/4207/Pub

9/25/03 McGraw-Hill
Other configurations: Diode Logic
• Diodes can with resistive loads to implement
simple logic gates
Diode OR gate Diode AND gate

9/25/03 McGraw-Hill
Diode Transistor Logic
• Since diode gates are limited to AND and OR

functions, the diodes can be combined with
transistors to complete the basic logic functions
such as the following NAND gate

9/25/03 McGraw-Hill
Using Transistors in Place of a Resistor
• NMOS load w/ a)
gate connected
to the source
b) gate connected
to ground
c) gate connected
to VDD
d) gate biased to
linear region
e) a depletion
mode NMOS
Note that a) and b) are
not useful

9/25/03 McGraw-Hill
Static Design of the NMOS Saturated
Load Inverter
Schematic for a NMOS Cross-section for a NMOS

saturated load inverter saturated load inverter

9/25/03 McGraw-Hill
NMOS Inverter with a Depletion-mode
Load
• With the addition of a
depletion-mode NMOS
(VTH < 0V), it is possible
to configure an inverter
as shown
• VGSL = 0 V for this
configuration meaning
that ML is always
operating in saturation

9/25/03 McGraw-Hill
Layout of the NMOS Depletion-Mode
NOR and NAND Gates

9/25/03 McGraw-Hill
NMOS Inverter Summary
• Resistive load inverter takes up too much area for and IC

design
• The saturated load configuration is the simplest design, but
VH never reaches VDD and has a slow switching speed
• The linear load inverter fixes the speed and logic level
issues, but it requires an additional power supply for the
load gate
• The depletion-mode NMOS load requires the most
processing steps, but needs the smallest area to achieve the
highest speed, VH = VDD, and best combination of noise
margins
9/25/03 McGraw-Hill
Typical Inverter Characteristic
Inverter w/ Saturated Linear Inverter w/

Resistor Load Load Depletion-
Load Inverter Inverter Mode Load
VH 5.0 V 3.4 V 5.0 V 5.0 V
VL 0.25 V 0.25 V 0.25 V 0.25 V
NML 0.34 V 0.32 V 0.02 V 0.69 V
NMH 1.43 V 0.69 V 2.78 V 2.25 V
Area (μm2) 9500 6.92 9.36 4.21

9/25/03 McGraw-Hill
Dynamic Response of Logic Gates
• An important figure of merit to describe logic

gates is their response in the time domain
• The rise and fall times, tf and tr, are measured at
the 10% and 90% points on the transitions
between the two states as shown by the following
expressions:
V10% = VL + 0.1ΔV
V90% = VL + 0.9ΔV = VH – 0.1ΔV

9/25/03 McGraw-Hill
Propagation Delay
• Propagation delay describes the amount of time between a

change at the 50% point input to cause a change at the
50% point of the output described by the following:
VH  VL
V50% 
2
• The high-to-low prop delay, τPHL, and the low-to-high prop
delay, τPLH, are usually not equal, but can be described as
an average value:
 PHL   PLH
P 
2
9/25/03 McGraw-Hill
Dynamic Response of Logic Gates

9/25/03 McGraw-Hill
Power Delay Product
• The power-delay product (PDP) is use as a metric

to describe the amount of energy required to
perform a basic logic operation and is given by the
following equation when P is the average power
dissipated be the logic gate:
PDP  P P

9/25/03 McGraw-Hill
Static Power Dissipation
• Static Power Dissipation is the average power

dissipation of a logic gate when the output is in both
the high and low states
VDD I DDH  VDD I DDL
Pav 
2
• IDDH = current in the circuit for vO = VH
• IDDL = current in the circuit for vO = VL
• Since IDDH = 0 A for vO = VH:

VDD I DDL
Pav 
2
9/25/03 McGraw-Hill
Dynamic Power Dissipation
• Dynamic Power Dissipation is the power

dissipated during the process of charging and
discharging the load capacitance connected to the
logic gate
Charging Discharging
9/25/03 McGraw-Hill
• The energy delivered to the capacitor can be found by:
 VC (  )
ED  VDD  i (t )dt  CVDD  i (t ) dvC  CV 2

DD
0 VC ( 0 )
• Energy stored by the capacitor with C=Q/V is:
Q
Q q Q 2 CV 2
ES   Vdq   dq  1  DD
0 C 2 C 2
0
• The energy lost in the charging and discharging the C
through resistive elements is thus given by:
2
CVDD
E L  E D  ES 
2
9/25/03 McGraw-Hill
• The total energy lost in the charging and discharging

of the capacitor through resistive elements is given by:
2 2
CV CV
ETD  DD
 DD
 CV 2
DD
2 2
• Thus it can be seen that for every cycle (frequency)
that the gate is changed, the dynamic power
dissipation is given by:
PD  CV 2
DD f

9/25/03 McGraw-Hill
Power Scaling in MOS Logic
• By reducing the W/L of the load and switching

transistors of an inverter, it is possible to reduce
the static power dissipation by the same factor
without sacrificing VH and VL. This same concept
works for increasing the power which will
increase the dynamic response. For resistive load,
the switching transistor W/L and the load resistor
should be scaled up or down by the same factor.

9/25/03 McGraw-Hill
Power Scaling in MOS Logic
a) Original Saturated Load Inverter

b) Saturated Load inverter designed to operate at 1/3 the power
c) Original Depletion-Mode Inverter
d) Depletion-mode inverter designed to operate at twice the power
9/25/03 McGraw-Hill
Dynamic Behavior
Capacitance in MOS Logic Circuits
• The MOS device has the
capacitances CSB, CGS, CDB, and
CGD that need to be considered
for dynamic response analysis,
but depending on the
configuration, some of them
will be shorted out as seen in
the first figure
• The capacitance seen at a node

can be lumped together as seen
in the second figure

9/25/03 McGraw-Hill
Fan-out Limitations
• Static design constraints are not usually important

for MOS logic circuits since they normally drive
capacitive loads (i.e. the gate of a MOS)
• As the number of gates the output (fan-out) of a
logic device has to drive, the load capacitance
increases, and the time response decreases
• This notion implies that the fan-out that a logic
circuit can drive will be limited to time delay
tolerances of the circuit

9/25/03 McGraw-Hill
Dynamic Response of the NMOS
Inverter with a Resistive Load
• The rise and fall times and propagation delays are
given by the relationships:
t r  t f  2.2 RC
 PLH   PHL  0.69 RC
where R and C are the resistance and capacitance
seen at the output

9/25/03 McGraw-Hill
• There are four
important times
that need to be
considered when
characterizing the
dynamic response
of a logic circuit
which are denote
t1 – t4 in the figure

9/25/03 McGraw-Hill
• It is also possible to calculate τPHL and tf by a
piecewise analysis technique, and are given by the
following equations:
   VH  VTNS   2VTNS 
 PHL  t3  (t3  t 2 )  t 2  RonS C ln 4   1  
   VH  VL   V H  VTNS 
  VH  2VTNS  0.9V  2VTNS  0.1V  


t f  t 4  t1  RonS C ln  2  
VH  0.9V 
   VH  VTNS  

9/25/03 McGraw-Hill
Comparison of Load Devices
• The current has

been normalized
to 50 μA for
vo=VOL=0.25 V
is the figure for
the various
types of
inverters

9/25/03 McGraw-Hill
• Body effect degrades the performance of the load

device
• The saturated load devices have the poorest τPLH
since they have the lowest load current delivery
• The saturated load devices also reach zero current
before the output reaches 5 V
• The linear load device is faster than the saturated
load device, but still slower than the resistive load
inverter.
• The fastest τPLH is from the depletion-mode device
9/25/03 McGraw-Hill
Simulated fall times for Simulated rise times for

a 0.1 pF load a 0.1 pF load
9/25/03 McGraw-Hill
PMOS Logic
• PMOS logic circuits predated NMOS logic circuit, but were replaced
since they are usually operate at slower speeds (note the change in the
power supplies and that VL = -5V, VH=-0.25 for (a,c,d), VL = -4V,
VH=-0.25 for b)
Resistive Load Saturated Load Linear Load Depletion-mode Load

9/25/03 McGraw-Hill
PMOS
• For VGS VTP , transistor is off.

• For more negative vGS, drain
current increases in magnitude.
• PMOS is in triode region for
small (neg) values of VDS and in
saturation for larger (neg) values.

9/25/03 McGraw-Hill
9/25/03 McGraw-Hill
PMOS NAND and NOR Gates
NOR Gate NAND Gate

9/25/03 McGraw-Hill
Silicon Art
• In the earlier days of IC design, chip designers

were allowed to artistically express themselves on
the wafer by creating images with various
processing steps
• However, today’s modern foundries have stopped
this since the graphics did not pass the design
rules and were causing fabrication problems

9/25/03 McGraw-Hill
Silicon Art Examples

9/25/03 McGraw-Hill

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Chapter 6

Introduction to Digital Electronics

Microelectronic Circuit Design

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 1

• The output will consist of either a 0 (low) or a 1 (high)

• The most basic digital building block is the inverter

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 2

The ideal inverter has the following voltage transfer characteristic

V+ and V- are the supply rails, and VH and VL describe

An inverter operating with power supplies at V+ and

• Noise margins represent “safety margins” that

NML = VIL – VOL

NMH = VOH – VIH

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 8

• MOS transistors (both PMOS and NMOS) can be

• The circuit designer is limited to altering circuit

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 10

• The resistor R is used

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 11

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 13

• First the value of the current through the resistor

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 14

• For vI = VL = 0.2V, the transistor’s vGS will be less

• The NMOS resistive load

When the NMOS resistive load inverter’s output is

• The following equations can be used to determine

To find VIL & VOH

To find VIH and VOL

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 19

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 21

Use this design as the reference inverter for complex

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 22

Two-input NOR gate Simplified switch model for

Two-input NAND gate

Simplified switch model

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 24

• The NAND switching transistors can be sized based on the

• The technique used to calculate the size of the load

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 26

An advantage of NMOS technology is that it is simple to design

The circuit in the

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 27

• There are two ways to find the W/L ratios of the

1) Using the worst case (longest) path and choosing the

2) Partitioning the circuit into series sub-networks, and

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 28

The figure on the left

The figure on the right

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 29

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 30

(a) What is the logic function?

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 31

a) Find logic function

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 32

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 33

Diode OR gate Diode AND gate

Jaeger/Blalock Microelectronic Circuit Design Chap 6 - 34