Topic 6

Design Methodology
Sivadev Nadarajah
COURSE LEARNING OUTCOMES (CLO)

Upon completion of subtopic 6.1, students should be able to:

• 6.1 Know hierarchy design
– 6.1.1 Define hierarchy design
– 6.1.2 Describe the design abstraction level:
• a. System
• b. Module
• c. Gate
• d. Circuit
• e. Device
Hierarchy Design

• Design is defined as
– An iterative process that refines an "idea" to a
manufacturable device.
• Hierarchy
– an arrangement or classification of things
according to relative inclusiveness.
• Hierarchy Design
– A “divide and conquer” technique involves
dividing a module into sub- modules and then
repeating this operation on the sub-modules until
the complexity of the smaller parts becomes
manageable.
Hierarchy Design

• Hierarchy - different levels of layout on a chip

– Country (Malaysia)  State (Perak)  City (Ipoh)
 Neighborhood (Taman Cempaka)
– Chip  cluster  unit  block  cell
• Child Cell
– cell contained in larger cell is child of that cell
• Parent Cell
– cell containing smaller cells is parent of those cells
• Hierarchy organizes & simplifies complexity
Hierarchy Design
Design Abstraction Level

• Has 5 levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
Design Abstraction Level

• System
– The overall design and functions is identified.
• Module
– The overall function is broken down to smaller and
manageable sub function
• Gate
– Each sub function is appropriate gates
• Circuit
– Convert each gate into CMOS schematic
• Device
– Create the layout for the schematic.
Design Abstraction Level (Example)

• LEVEL 1- System
– Create a design for a 2-input 1-output2 Multiplexer

• LEVEL 2- Module
– 2 Input (D1 & D2), 1 Outputs (Y), 1 Enable, 1 Select (S), 1 Vcc
and 1 Gnd – total of terminals = 7
Design Abstraction Level (Example)

• LEVEL 3 - Gate
– Example: Each MUX needs 1 Inverter and 3 NAND Gate
Design Abstraction Level (Example)

• LEVEL 4 - Circuit
– Convert each gate into CMOS schematic

• LEVEL 5 - Device
– Create the layout for the schematic using L-Edit.
End of Sub Topic 6.1

• Questions and Answers

COURSE LEARNING OUTCOMES (CLO)

Upon completion of subtopic 6.2, students should be able to:

• 6.2 Understand the design methodology
– 6.2.1 Explain the design methodologies used in designing integrated circuit based
on the tree diagram that comprises of; standard IC, specific custom IC, Full-
custom IC, semi-custom IC, gatearray,standard cell, and programmable logic
device (PLD)
– 6.2.2 Explain the application-specific integrated circuit (ASICs)
– 6.2.3 Explain the advantages of ASICs over standard IC
– 6.2.4 Explain semi-custom IC design methodology
– 6.2.5 Explain full-custom IC design methodology
– 6.2.6 Compare semi-custom design methodology and full-custom design
methodology
COURSE LEARNING OUTCOMES (CLO)

Upon completion of subtopic 6.2, students should be able to:

• 6.2 Understand the design methodology
– 6.2.7 Explain the advantages and disadvantages of semi-custom design
methodology and full-custom design methodology
– 6.2.8 Explain types of semi-custom design methodologies:
• a. Gate-array
• b. Standard cell
• c. Programmable Logic Devices (PLD)
– 6.2.9 Explain gate-array including the elements below:
• a. Basic elements in CMOS gate-array
• b. Advantages and disadvantages of this methodology
– 6.2 10 Explain Standard cell covering the contents below:
• a. Cell library and Array Block
• b. Advantages and disadvantages of this methodology
Design Methodology Tree Diagram
Standard Integrated Circuits

• Standard IC are integrated circuits designed

and fabricated for general purpose use.
• Standard IC is available in the market at a very
low cost.
• Examples of standard ICs:
– 74 - SERIES TTL,
– 4000 - SERIES CMOS,
– 741 OP-AMP, 555 TIMER,
– INSTRUMENTATION AMPLIFIER, MEMORY,
MICROCONTROLLER, etc.
Example of Standard IC

• 74-TTl Series

• 4000-CMOS
Seires
Example of Standard IC
ASIC

• Progress in the fabrication of IC's has enabled

the designer to create fast and powerful
circuits in smaller and smaller devices.
• This also means that we can pack a lot more
of functionality into the same area.
• The biggest application of this ability is found
in the design of ASICs.
ASIC

• ASICs stands for :

– Application Specific Integrated Circuits
• ASICs are IC's that are created for specific
purposes - each device is created to do a
particular job.
• ASICs are produced for only one or a few
customers or applications.
• ASICs are devices made for a specific
application such as a mobile phone.
Example of ASIC
Advantages of ASIC
Advantages Disadvantages
Compact and Lightweight Potential of design failure
Fast Delivery Not off-the-shelf availability
Low Power Consumption Specification, design, testing and
documentation phases are needed
Custom-Made - Customer’s Circuit High cost per IC
Higher initial cost for development
Comparison between ASIC and
Standard IC
Standard IC ASIC
Low cost Good security in design- each
manufacturer has different design
Availability off-the-shelf Efficient use of board – reduce the
area, weight and power of circuit
Low design cost Higher reliability because less external
circuit
Proven component reliability Optimized performance and external
component cost
Multiple sourcing – many For a particular special function that
manufacturers cannot be done by standard IC
For general purpose High design cost and cycle time
Semi-custom Design Methodology
• Semi-custom IC design is a methodology for making an
integrated circuit which
– a portion of the circuit function is predefined and unalterable,
– while other portions can be configured to meet the designer's
specific needs.
• Designers have the capability of designing application-
specific circuits themselves, using either
– standard cell libraries or
– preconfigured arrays.
• In semicustom IC, all of the logic cells are predesigned and
some of the mask layers are customized.
• Using predesigned cells from a cell library makes our lives
as designers much easier and faster.
• Therefore, semi-custom ICs are the less expensive to
manufacture and to design.
• Examples : ethernet chip, hard disk controller
Full-custom Design Methodology
• Full-custom IC design is a methodology for designing
integrated circuits by specifying the layout of each
individual transistor and the interconnections
between them.
• Full-custom IC design potentially maximizes the
performance of the chip, and minimizes its area,
but is extremely labor-intensive to implement.
• Full-custom IC design is limited to ICs that are to be
fabricated in extremely high volumes, notably
certain microprocessors and a small number of ASICs.
• Time taken to design IC is longer and slow.
• A full-custom IC includes all logic cells that are
customized and all mask layers that are customized.
• Therefore, full-custom ICs are the most expensive to
manufacture and to design.
• Example : microprocessor.
Comparison of Full vs. Semi Custom IC

Full Custom Semi Custom

Small Die size –
High component density
Flexible design –
Ability to integrated analog and digital
components
Optimized Performance –
Ability to operate at high frequency
Increase in design time –
Time consuming design
High cost and effort –
In design and manufacturing
High complexity and risk –
Design is exposed to errors
• Advantages – in blue
• Disadvantages – in red
Die size smaller than standard IC but
larger than Full Custom IC
Limited ability to integrate analog and
digital components
Lower performance
Rapid turn around – faster design to
production time
Simplified verification
Less complexity and risk
Semi-Custom – Gate Array
• Gate arrays are integrated circuits containing large
numbers of digital gates or transistor cells, which can
be interconnected in different ways to implement
various logic functions.
• Gate array consists of transistors, usually arranged in two
pairs of PMOS and NMOS.
• Wafers containing these gate arrays have been processed
up to all steps except the metallization layers.
• Using computer-aided-design tools, only the metallization
layer patterns are required to be generated from the
circuit specification, and the fabrication time can be very
short.
• Gate arrays can have several metallization layers to
facilitate interconnection.
• ASIC vendors offer a selection of gate array cells, with a
different total numbers of transistors on each cell, for
example, gate arrays with 50k-, 75k-, and 100k-gates.
Semi-Custom – Gate Array
Semi-Custom – Gate Array
Semi-Custom – Gate Array
Semi-Custom – Gate Array

• Example;
– Create a 2-input NAND Gate using Gate Array.
– 2-input NAND Gate schematic.
Semi-Custom – Gate Array
Semi-Custom – Gate Array
Semi-Custom – Gate Array
Semi-Custom – Gate Array
Advantage Disadvantage
Cheaper process Advanced CAD software is required in
design
Speedy design Not all of the gates offered by the
vendor are being used in the design
Low power dissipation IC Optimum circuit performance cannot
be achieved
Semi-Custom – Standard Cell
• Standard cell design involves the use of pre-designed
standard cell that has been and stored in database.
• Standard cell consists of simple circuit such as
– Basic logic gates; e.g. inverter AND, OR, XOR, XNOR, flip-flop
and latches
– complex circuit such as register, adder, ROM and RAM.
• Design is carried out by simply using the pre-designed
cells from the library and then connect the cells so that
certain functions can be implemented.
• To facilitate placement and routing, the standard cells are
designed to have
– equal height but
– variable widths,
• The final IC layout will have a regular pattern with rows of
cells and interconnect routing running between the rows.
Semi-Custom – Standard Cell

• The physical layout of Standard Cell consist of

2 divisions
– Cell Library
– Array Block
• Cell Library are
– collection of low-level electronic logic functions
such as AND, OR, INVERT, NAND, NOR, flip-flops
and latches.
– Has fixed-height, variable-width full-custom cells.
– which enables them to be placed in rows, easing
the process of automated digital layout.
– typically optimized full-custom layouts, which
minimize delays and area.
Semi-Custom – Standard Cell

• Array Block are

– the block containing the complex circuit such as
register, adder, ROM and RAM
– Allocated at the corners
– Has accessibility to routing lines
• All around the IC there are Input and Output
pad to connect to the IC packaging leads.
Semi-Custom – Standard Cell
Semi-Custom – Standard Cell
Advantages
The Percentage Of Using All Gates Are
Very High
Produce High Performance Chip
The Optimum Chip Size Can Be
Achieved
The Chip Can Be Guaranteed To
Function Well For The First Time It Is
Designed
Disadvantages
The Standard Cells Must Be Designed
To Have Equal Height, So That The Final
IC Layout Will Have A Regular Pattern
High Design Cost
Design Cannot Be Done If The Required
Cell Is Not Available In The Library
End of Sub Topic 6.2

• Questions and Answers

COURSE LEARNING OUTCOMES (CLO)

Upon completion of subtopic 6.3, students should be able to:

• 6.3 Understand Programmable Logic Devices (PLD)
– 6.3.1 Explain Programmable Logic Devices (PLD)
– 6.3.2 Illustrate PLD block diagram and the contents
– 6.3.3 Explain the advantages of using PLD compared to standard IC and Custom
IC
– 6.3.4 Explain the architecture of PROM, PAL and PLA using appropriate diagrams
– 6.3.5 Explain the methods of programming device using schematic entry, Boolean
expression and truth table
– 6.3.6 Explain PLD programming language: low level and high level
– 6.3.7 Explain large-Scale PLD: FPGA and CPLD
Semi-Custom - PLD

• Programmable Logic Devices (PLDs) are ICs

with
– a large number of gates and
– flip flops
• These can be configured with basic software
to perform a specific logic function or
perform the logic for a complex circuit.
Semi Custom - PLD
Semi Custom - PLD

• PLD does not require a common mask layout

in design.
• The design time is shorter.
• It consists of a large block of internal
connections that can be a programmed.
• Programming can be done at different stages:
– at the earliest, it is programmed by the
semiconductor vendor (standard cell, gate array).
– by the designer prior to assembly or field
deployment.
– by the user in circuit.
Semi Custom - PLD

• Advantages Of PLD Compared To Standard IC

& Other ASIC are
– Reduced Complexity Of Circuit Boards
• Lower Power Requirements
• Less Board Space
• Simpler Testing Procedures
– Higher Reliability
– Design Flexibility
Semi Custom - PLD

• Some of the PLD manufactures

Semi Custom - PLD

• General Block Diagram of PLD

 Semi Custom - PLD

• Types of PLD
Programmable Logic Device
(PLD)

Simple Programmable Field Programmable Complex Programmable

Logic Device Gate Array Logic Device
(SPLD) (FPGA) (CPLD)

Programmable Read Programmable Array Programmable Logic

Only Memory Logic Array
(PROM) (PLA) (PAL)
SPLD - PROM

• First and Simplest PLD

• Has
– Predefine AND array (fixed by manufacturer)
– Programmable OR array (can be programmed by user)
SPLD - PLA

• Opposite of PROM, has

– Programmable AND array
– Predefine OR array
SPLD - PAL

• More flexible because it has

– Programmable AND array
– Programmable OR array
SPLD – PROM, PLA and PAL
PLD – Programming Method
• Three Methods Of Programming PLD:
– Schematic Capture.
– Boolean Expression Using Hardware Description Language (HDL).
– Truth Table / State Diagram.
• Boolean Expression
– All logic expression can be represented using gate AND, OR and NOT.
– This method translates the equations into schematic of gate where the
inversion (NOT gate), addition (OR gate) and multiplication (AND gate)
are used.
– HDL is used to program the optimized expression on to the chip
• Truth Table
– Obtain the relationship between the input and the output in the form
of Truth Table.
– The truth table is translated into equivalent logic then programmed.
• Schematic capture
– A schematic diagram is drawn and converted to logic input / output.
– These logics are programmed into the Chip
PLD-Programming Language

• The language used is know as HDL (Hardware

Description Language)
• Two level of Language Used
– High Level
• VHDL (Very High Speed IC HDL)
• Verilog
– Low Level
• CUPL (Universal Compiler For Programmable Logic)
• PALASM(PAL Assembler)
• ABEL (Advanced Boolean Expression Language)
PLD-Programming Language

• VHDL (Very High Speed IC HDL)

– used in electronic design automation to describe
digital and mixed-signal systems such as field-
programmable gate arrays (FPGA) and complex
programmable logic devices (CPLD).
– VHDL was originally developed by the U.S
Department of Defense.
• Verilog
– one of the first modern HDL to be invented by
Prabhu Goel and Phil Moorby in 1984.
PLD-Programming Language
• CUPL (Universal Compiler For Programmable Logic)
– released in September 1983.
– the first commercial design tool that supported multiple PLD
families.
– Initial release was for the IBM PC and MS-DOS, and written
in the C programming language
– In 1986, PCAD's schematic capture package was used as a
GUI for CUPL.
• PALASM(PAL Assembler)
– was developed by John Birkner in the early 1980s and
written in FORTRAN IV on an IBM 370/168.
• ABEL (Advanced Boolean Expression Language)
– Data I/O Corporation released ABEL in April, 1984 by Michael
Holley, Mike Mraz, Gerrit Barrere, Walter Bright, Bjorn
Freeman-Benson, Kyu Lee, David Pellerin, Mary Bailey, Daniel
Burrier and Charles Olivier.
– ABEL is now own and is a part of the Xilinx Webpack tool
suite.
Complex Programmable Logic Device
(CPLD)
• CPLDs evolved from PAL\PLAs as chip
densities increased, it was natural for the PLD
manufacturers to evolve their products into
larger parts (several tens of thousands of
gates).
• Larger sizes of CPLDs allow either more logic
equations or more complicated designs to be
realized.
CPLD

• Typical architecture of CPLD

CPLD - Applications

GPS Navigation Systems PDA

- Hard disk controller

- GPIO interface - LCD Timing Control
- Timing configuration - GPIO Expansion
- Power Management
- Level Shifting
 CPLD - Applications

GSM Phone Printer

- Controller and interface conversion

- Interface expansion
- Simple glue logic
- Keypad scanner
- Logic consolidation
Field Programmable Gate Array (FPGA)

• This device is similar to the gate array, with

the device shipped to the user with general-
purpose metallization pre-fabricated, often
with variable length segments or routing
tracks.
• The device is programmed by turning on
switches which make connections between
circuit nodes and the metal routing tracks.
• The connection may be made by a transistor
or by an anti-fuse.
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA)

• Configurable Logic Block (CLB)

– Degree of ‘complexity’ is called the granularity
– Can implement a single logic function (fine
grained)

– Or a block of logic functions (course grained)

– Also, may incorporate registers (‘D’ Type FF’s)

Comparison between CPLD & FPGA
Comparison between CPLD & FPGA
End of Sub Topic 6.3

• Questions and Answers

COURSE LEARNING OUTCOMES (CLO)

Upon completion of subtopic 6.4, students should be able to:

• 6.4 Apply the knowledge of PLD architecture in constructing PLD
array structure
– 6.4.1 Construct PLD circuit for a given logic functions using:
• a. PROM
• b. PAL
• c. PLA
PLD Example

• Construct PLD circuit for F0, F1, F2, F3 using:

– PROM
– PAL
– PLA
• Given:

F 0  A  BC F 2  BC  AB

F 1  AC  AB F 3  BC  A
PLD Example - PROM
A B C

F 0  A  BC F 1  AC  AB
Predefined
F 2  BC  AB F 3  BC  A
Programmable
PLD Example - PAL
A B C

F 0  A  BC F 2  BC  AB
Predefined
F 1  AC  AB F 3  BC  A
Programmable
PLD Example - PLA
A B C

F 0  A  BC F 2  BC  AB
Predefined
F 1  AC  AB F 3  BC  A
Programmable
PLD Exercise

• Construct PLD circuit for F0, F1, F2, F3 using:

– PROM
– PAL
– PLA
• The boolean equation are
– 𝐹0 = 𝐴 + 𝐵 + 𝐶
– 𝐹1 = 𝐴 𝐶 + 𝐵𝐶 + 𝐴 𝐵 𝐶
– 𝐹2 = 𝐴𝐵𝐶 + 𝐵
– 𝐹3 = 𝐴 + 𝐵 + 𝐴 𝐵 𝐶
PLD Exercise-PROM Predefined
A B C Programmable
PLD Exercise- PAL
A B C

Predefined
Programmable
PLD Exercise- PLA
A B C

Programmable
End of Sub Topic 6.4

• Questions and Answers