Address Decoder

Address Decoder
• Normally, microprocessor is connected to
several devices
• However, only one device can communicate
with the processor at one time leaving other
devices at high impedance
• To ensure this condition is established,
address decoder is introduced
• With this decoder, there will not be any
devices fighting for control of common wire
which may cause damaging to current flow
 Address Decoder
• The role of the address decoder is to ensure one device can
communicate with the processor at one time.
• This is done by placing all unselected devices into high
impedance condition by deactivate enable pin of each device
• There are two type of decoders
– Full address decoder (FAD)
• All address buses of processor must be connected
– Partial address decoder (PAD)
• Only a few selected address buses are connected
• PAD using combinational circuit
• PAD using MSI chip
• Advantage of PAD
– Less hardware design
– Less expensive
• Disadvantage of PAD
– More than one address can activate a device
– Future expansion of memory is difficult
• Nowadays, almost all microprocessor-based system
are designed using the MSI chip to produce simple,
cost-effective and efficient system
 Full Address Decoder
Design Procedure
• Procedure to design the address decoder for memory
• For each memory device, determine the entire range of address
– The first address
– Size of memory
– The last address
• For each memory device, determine the number of address lines
connected to memory
– Determine the total address lines of the device
– The lower address lines of processor are connected directly to memory
– The rest of address lines are connected to the address decoder
• Design decoder circuit
 Partial Address Decoder
Design Procedure
• Procedure to design the address decoder for memory
• For each memory device, determine the entire range of address
– The first address
– Size of memory
– The last address
• For each memory device, determine the number of address lines
connected to memory
– Determine the total address lines of the device
– The lower address lines of processor are connected directly to memory
– The rest of address lines can be considered to design the address decoder
– Normally, higher address lines are used to distinguish devices
– The less number of lines involved, the simple the decoder circuit
 Exercise 1
• CPU ATMega8515
• Address bus 16 bit
• External RAM #1 8KB at 8000h
• External RAM #2 8KB at C000h
• Design Full Address Decoder & Partial Address
Decoder
 Exercise 1
• RAM #1
– Beginning Address at 8000H
– Size 8KB
• 8KB = 2000H
• From 0000H to 1FFFH
– Ending Address at 8000H + 1FFFH = 9FFFH
 Exercise 1
• RAM #2
– Beginning Address at C000H
– Size 8KB
• 8KB = 2000H
• From 0000H to 1FFFH
– Ending Address at C000H + 1FFFH = DFFFH
 Exercise 1
• Address Bus 16bit : 216 = 64KB
– From 0000H to FFFFH
– Address notation from A0 to A15 (LSB to MSB)
• RAM #1: 8K - 8000H to 9FFFH
– Address lines required: 2 x  8K
x log(2)  log(8K )
log(8K )
x  13
log(2)
– Address from A0 to A12
 Exercise 1
• RAM #1: 8K - C000H to DFFFH
– Address lines required: 2 x  8K
x log(2)  log(8K )
log(8K )
x  13
log(2)
– Address from A0 to A12
• Address lines left for address decoding:
– 16 – 13 = 3 lines
– A13 to A15
 Exercise 1
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

RAM#1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 9FFFH
RAM#2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000H
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 DFFFH

Used for address decoder

Full address decoder: Partial address decoder:

CSRAM#1 = A15 and A̅14 and A̅13 CSRAM#1 = A̅14
CSRAM#2 = A15 and A14 and A̅13 CSRAM#2 = A14
 Exercise 2
• CPU ATMega8515
• Address bus 16 bit
• External RAM #1 8KB at 4000h
• External RAM #2 16KB at 8000h
• Design Full Address Decoder & Partial Address
Decoder
 Exercise 2
• RAM#1
– Size: 8K : 0000H – 1FFFH
– Address : 8K : 4000H – 5FFFH
– #Address lines = 13
• RAM#2
– Size: 16K = 4000H : 0000H – 3FFFH
– Address : 16K : 8000H – BFFFH
– #Address lines = 14
• #Address line used for decoding?
 Example #3
• A small system need to interface memory to a
μP-based system. The address ranges are:
– ROM: $0000 - $07FF
– RAM: $2000 – $2FFF
– I/O: $A000 - $A03F
• Design the memory address decoder
using Partial Addressing method.
 Example #4
• A μP system needs to be built with the
following specifications:
– EPROM: 4kB needed, start address $1000.
– SRAM: 2kB needed, start address $2000.
– I/O, start address $3000.
• Design the decoder using partial address
decoding.
Address Decoding Example
with 74LS138
74LS138 Truth Table