Analog-to-Digital Conversion

Terminology
analog: continuously valued signal, such as temperature or
speed, with infinite possible values in between

digital: discretely valued signal, such as integers, encoded in

binary

analog-to-digital converter: ADC, A/D, A2D; converts an analog

signal to a digital signal

digital-to-analog converter: DAC, D/A, D2A

An embedded system’s surroundings typically involve many

analog signals.
 Analog-to-digital converters
Vmax = 7.5V 1111 4 4
7.0V 1110
6.5V 1101 3 3

analog output (V)

analog input (V)
6.0V 1100
5.5V 1011
2 2
5.0V 1010
4.5V 1001
4.0V 1 1
1000
3.5V 0111
3.0V 0110 time time
t1 t2 t3 t4 t1 t2 t3 t4
2.5V 0101
2.0V 0100 0100 0110 0110 0101 0100 1000 0110 0101
1.5V 0011 Digital output Digital input
1.0V 0010
0.5V 0001
0V 0000

proportionality analog to digital digital to analog

Embedded Systems Design: A Unified

Hardware/Software Introduction, (c) 2000 Vahid/Givargis
 Proportional Signals
Simple Equation Vmax 1..1 = 2n-1

Assume minimum voltage of 0 V.

Vmax = maximum voltage of the
analog signal
a = analog value …
n = number of bits for digital
encoding
2n = number of digital codes
M = number of steps, either 2n or 2n – 1
d = digital encoding

a / Vmax = d / M 0V 0..0 = 0
 Resolution
Let n = 2
Vmax 3=11

M = 2n – 1 r

3 steps on the digital scale 3=11

d0 = 0 = 0b00
2=10
dVmax = 3 = 0b11

M = 2n 2=10

4 steps on the digital scale

1=01
d0 = 0 = 0b00
1=01
dVmax - r = 3 = 0b11 (no dVmax )

r, resolution: smallest analog change

0V 0=00 0=00
resulting from changing one bit
 DAC vs. ADC Vmax

DAC: x0
x1
n digital inputs for digital encoding d DAC
…
analog input for Vmax Xn-1
a

analog output a

ADC:

Given a Vmax analog input and an analog input a, how does the
converter know what binary value to assign to d in order to
satisfy the ratio?
– may use DAC to generate analog values for comparison with a
– ADC “guesses” an encoding d, then checks its guess by inputting d
into the DAC and comparing the generated analog output a’ with
original analog input a
– How does the ADC guess the correct encoding?
 ADC: Digital Encoding
Guessing the encoding is similar to finding an item in a list.

1. Sequential search – counting up: start with an encoding of

0, then 1, then 2, etc. until find a match.
• 2n comparisons: Slow!
2. Binary search – successive approximation: start with an
encoding for half of maximum; then compare analog result
with original analog input; if result is greater (less) than the
original, set the new encoding to halfway between this one
and the minimum (maximum); continue dividing encoding
range in half until the compared voltages are equal
• n comparisons: Faster, but more complex converter

 Takes time to guess the encoding: start conversion input,

conversion complete output
 ADC using successive
approximation
• Given an analog input signal whose voltage
should range from 0 to 15 volts, and an 8-bit
digital encoding, calculate the correct encoding for
5 volts. Then trace the successive-approximation
approach to find the correct encoding.
• Assume M = 2n – 1
a / Vmax = d / M
5 / 15 = d / (256 - 1)
d = 85 or binary 01010101
 ADC using successive
approximation
Step 1-4: determine bits 0-3

½(Vmax – Vmin) = 7.5 volts

0 0 0 0 0 0 0 0
Vmax = 7.5 volts.
½(7.5 + 0) = 3.75 volts
0 1 0 0 0 0 0 0
Vmin = 3.75 volts.

½(7.5 + 3.75) = 5.63 volts 0 1 0 0 0 0 0 0

Vmax = 5.63 volts

½(5.63 + 3.75) = 4.69 volts 0 1 0 1 0 0 0 0

Vmin = 4.69 volts.

Embedded Systems Design: A Unified

Hardware/Software Introduction, (c) 2000 Vahid/Givargis
 ADC using successive
approximation
Step 5-8: Determine bits 4-7

½(5.63 + 4.69) = 5.16 volts 0 1 0 1 0 0 0 0

Vmax = 5.16 volts.
½(5.16 + 4.69) = 4.93 volts 0 1 0 1 0 1 0 0
Vmin = 4.93 volts.

½(5.16 + 4.93) = 5.05 volts 0 1 0 1 0 1 0 0

Vmax = 5.05 volts.
½(5.05 + 4.93) = 0 1 0 1 0 1 0 1
4.99 volts

Embedded Systems Design: A Unified

Hardware/Software Introduction, (c) 2000 Vahid/Givargis
 Constructing ADC

Analog State
input machine
Timing
control
Vmax SAR
DAC
Vmin BUF Digital
output

Comparator SAR

SAR: Successive
approximation register
 Bit Weight
Notice the concept of bit weight Digital Bit Bit Weight (V)
in the last example:
bit 7 = 7.5 V = 15/2 7 10/2 = 5
bit 6 = 3.75 V = 15/4
6 10/4 = 2.5
Each bit is weighted with an 5 10/8 = 1.25
analog value, such that a 1 in that
bit position adds its analog value 4 10/16 = 0.625
to the total analog value
3 10/32 = 0.313
represented by the digital
encoding. 2 10/64 = 0.157

Example: -5 V to +5 V analog 1 10/128 = 0.078

range, n=8 0 10/256 = 0.039
 Bit Weight
Example (continued): -5 V to Analog (V) Digital (hex)
+5 V analog range, n=8
-5 00

Digital numbers for a few analog -3.75 20

values -2.5 40
– Values shown increment by 6
bits (weight for bit position 5 -1.25 60
is 1.25 V) 0 80
– Maximum digital number
only approximates the 1.25 A0
maximum analog value in the 2.5 C0
range
• Try (-5) + sum of all bit 3.75 E0
weights
5-0.039 = 4.961 FF
 Terms & Equations
Offset: minimum analog value

Span (or Range): difference between maximum and minimum analog values
Max - Min
n: number of bits in digital code (sometimes referred to as n-bit resolution)

Bit Weight: analog value corresponding to a bit in the digital number

Step Size (or Resolution): smallest analog change resulting from changing one
bit in the digital number, or the analog difference between two consecutive
digital numbers; also the bit weight of the
Span / 2n (Assume M = 2n)

Let AV be Analog Value; DN be Digital Number:

AV = DN * Step Size + Offset = (DN / 2n )* Span + Offset
DN = (AV - Offset) / Step Size = (AV - Offset) * 2n / Span
MPC555 QADC64
QADC64 - Queued
Analog to Digital
Converter Module-64

• 16 analog channels via

internal multiplexing

• 10-bit ADC resolution

• Converts voltage to an
integer value (0-1023)

• Polling or interrupt driven

• Programmable channels
AN0-ANx
MPC555 QADC64
 MPC555 QADC64
CCW Table
CCW0 A CCW tells the ADC
CCW1 which channel to
AN0 scan and how long to
… sample the signal.
AN1
CCW63
AN2
AN3 ADC
QACR1: start a scan by setting SSE bit

QASR0: CF flag is set after conv is done

Result Table
Result0 A Result is stored for
Result1 each scan of a channel
when the conversion is
… complete.
Result63
 Scan Sequence and Conversion
• After the ADC is initialized, a sequence of scans is set up as a “queue”
in the CCW Table.
• Each channel to be scanned is added to the queue at successive
positions 0, 1, 2, etc. For example: CCW0, CCW1, CCW2, CCW3.
– An end-of-queue marker should be added at the next position.
• The ADC starts the scan and conversion when it is triggered by the
enable bit.
• The ADC reads the CCWs, one after another until end-of-queue is
reached, and for each CCW, it converts the signal on the specified
channel.
– A conversion on a channel stores a result in the respective position of the
Result Table, e.g., the result for CCW0 is stored at Result0, etc.
• When the scan and conversion is complete for all CCWs, then the ADC
sets the completion flag to 1. Now all digital results are available to be
read from the Result Table.
 QADC Interface
• Programmability using a queue
– Scan a few channels quickly
– Scan a channel multiple times
– Scan large number of channels
• QACR1 – QADC64 Control Register 1
o 16 bit register at 0x30480C
o SSE1 – bit 2 – Single Scan enable (bit 0 is MSb)
o MQ1 – bits 3-7
o Set to binary 00001 to identify Queue 1
• QASR0 – QADC64 Status Register 0
o 16 bit register at 0x304810
o ADC sets a flag when the conversion is done
o CF1 – bit 0 – Conversion Complete flag (bit 0 is MSb)
 QADC Interface
• CCW Table
o table of Conversion Command Words, where each command word specifies how
to perform a scan/conversion operation for an input channel
o CCW: 16 bit command word, starting at address 0x304A00
o A queue is a scan sequence of one or more input channels.
o A queue is started by a trigger event, which is a way to cause the QADC64 to
begin executing the command words.
o Each CCW requests the conversion of an analog channel to a digital result. The
CCW specifies the analog channel number, the input sample time, and whether
the queue is to pause after the current CCW.
CCW Table

16 bits
Entry
00 Begin Queue 1 0x304A00

0 5 6 7 8 9 10 15
Reserved P BYP IST CHAN

MSB LSB

n End Queue 1
 QADC Interface
• Total conversion time: initial sample time, final sample time, and resolution
time
o Initial sample time – time during which the selected input channel is driven by
the buffer amplifier onto the sample capacitor (disabled by means of the BYP bit
in the CCW)
o Final sampling period – time to set up DAC array
o Resolution period – time to convert voltage in the DAC array to a digital value
 QADC Interface
• Result Word Table
o table of Result Words, where each result word is the digital result of a
conversion
o Results from a sequence of conversions are placed in the Result Word
Table.
o RW: 16 bit result word, starting at address 0x304A80

• Programming the QADC:

– Reset the ADC queue
– Add (to the queue) each analog input channel to be scanned; e.g., four
channels, 0 through 3 (AN0-AN3)
– Add an end-of-queue marker to terminate the scan sequence
– Start a conversion on the ADC, which begins reading each analog
input and converting it to a digital value
 QADC64 Memory-mapping Layout
Bit 0 Bit 15 0x30 4A00
0x30 4800 Module Config. Reg.
64-entry 16-bit Conversion
0x30 4802 Test Reg. Command Word Table
0x30 4804 Interrupt Reg. (Configurable: one queue
0x30 4806 Port A Data Port B Data or two queues)
0x30 4808 Port A Direction Reg. 0x30 4A7E
0x30 480A Control Reg. 0 0x30 4A80
0x30 480C Control Reg. 1 64-entry 16-bit
0x30 480E Control Reg. 2 Result Word Table
0x30 4810 Status Reg. 0 64-entry, 16-bit
0x30 4812 Status Reg. 1 0x30 4AFE
The above is the memory-mapping for the 1st QADC64.
The 2nd QADC64 using different starting addresses.
 Programming QADC64

CCW Format: 6 7 8 9 10 11 12 12 14 15
P BYP IST CHAN

Example: Write a CCW into CCW table to scan channel

nChannel with no amplifier bypassing and 4-cycle initial sample
time (16 cycles in total).
nQueueVal = nChannel;
nQueueVal = nQueueVal & 0xFF3F;
nQueueVal = nQueueVal | 0x0040;
*(pCCWTable + nQueue) = nQueueVal;
The Control Registers
 The Status Registers

CF1 Queue1 completion flag

PF1 Queue1 pause flag
TOR1 Trigger over-run
QS Queue status
CWP Command word pointer
 Programming the ADC
• Initialize the QADC: reset queue to be
empty; set up interrupt driven mode,
interrupt levels, clock rate.
• Write into the command word queue (a
sequence of A to D conversion commands).
• In software triggered mode, initiate the
conversion by writing into QACR[SSE] bit.
• Monitor the conversion finished flag (CF).
• Read the results, and reset CF and PF flags.
 Programming QADC64
Example: Reset QADC64 by writing END-OF-QUEUE (63 in decimal) as
the first word of CCW table.

void QADCR64_Reset()
{
g_nNumChannels = 0;
QADCR64_SetQueue(0, QADCR64_END_QUEUE,
QADCR64_QCKL_MAX);
}

QADCR64_SetQueue: Given CCW entry index, CCW channel/end-of-

queue command, and final sample setting, write the corresponding CCW.
 Programming QADC64
Example: Start scanning in polling mode (interrupt disabled)
– Set up control register 1
void QADCR64_Start_Convert_Poll ()
{
unsigned short * pQACR1;
pQACR1 = (unsigned short *) 0x30480C;
// Bit 0 CIE1 Conversion Interrupt Enable 0
// Bit 1 PIE1 Pause Interrupt Enable 0
// Bit 2 SSE1 Single Scan Enable 1
// MQ=00001; software triggered single scan mode
*pQACR1 = 0x2100;
}
 Programming QADC64
Example: Determine if all conversions has finished
– Checking status register 0
unsigned short QADCR64_Is_Done()
{
unsigned short * pQASR0;
unsigned short nResult;
pQASR0 = (unsigned short *) 0x304810;
nResult = (*pQASR0 & 0x8000);
return nResult;
}
QADC Interrupt Sources
QADC64 Interrupt Programming
Set up interrupt register (0x304804 for 1st QADC)
0 45 9 10 15
IRL1 IRL2 Reserved

• IRL1, IRL2: interrupt levels for queue 1 and

queue 2, respectively.
• 5-bit interrupt level: QADC64 is IMB3 device
with interrupt level 0-31 (stored in UIPEND).
• Interrupt is generated at the completion of a CCW
if it is the end of queue or has the pause bit set.