DESIGN OF ADAPTIVE

NETWORK ON CHIP USING

VLSI TECHNOLOGY

Presented by Guided by
Mr.K.Ashokkanna B.E., Mrs.S.Selvi M.E.,(Ph.D).,M.I.S.T.E
Register No:950511419003 Assistant Professor & ECE HOD
 ABSTRACT

 Network-on-chip (NoC) designs are based on a compromise

among latency, power dissipation, or energy, and the balance
is usually defined at design time. However, setting all
parameters, such as buffer size, at design time can cause either
excessive power dissipation (originated by router under
utilization), or a higher latency.
 Networks-on-chip (NoCs) have emerged as a promising on-
chip interconnect for future multi/many-core architectures as
NoCs are able to scale communication links with the growing
number of cores.
 We propose a new adaptive routing algorithm for 8-port router
Architecture.
 ABSTRACT(CONT…)

 This project propose the new router topology which is used to

reduce the network routing time,and it is an suitable alternate
to network design and implementation.
 The Proposed Network-On-Chip Multi port Router can be
modelled using Verilog HDL and simulated using Modelsim
software.
 NODE DESIGN
Signal arrives

Packet passed
Incoming packet Signal leaves
warning

Packet from Signal from

ipsaY ipsY

signal Pass packet to opsX

 DECISION MAKING MODULE

packet
Decisio
DA DA[i]
Extractor

RECEIVING-ADDRESS FLAG

RA[i]

clock

Address Receiving Receiving longitudinal

Received latitudinal flag
flag flag
 PACKET COUNTER MODULE(PCM)

 The PCM strips the destination address from the packet.

 It counts the incoming packet bits and sets the RECEIVING-

ADDRESS flag when the first bit of the address is read.

ADDRESS COUNTER MODULE(ACM)

 The ACM keeps the track of the number of address bits that have
been read.

 It indicates which portion of the address is being received(latitude or

longitude) and if the entire address is received,it sets the ADDRESS-
RECEIVED flag.

 When the ADDRESS-RECEIVED flag is set, the IPS is told to keep

the packet.
 ROUTER ADDRESS PIPELINE(RAP)

 The RAP stores the router address and pipes it our serially so that it can be
compared with the incoming destination address.

 The Router address is static value,and is kept in non-volatile memory for

long term storage.

ADDRESS DIFFERENTIATION MODULE(ADM)

 The ADM simply compares the i-th bit of the destination address to the i-th
bit of the router address as the destination address is read in to the DMM.

 If the DA does not equal to RA,the ADM tells the incoming packet
storage(IPS) module to destroy the stored packet.
ARCHITECTURE OF ROUTER
 LIVELOCK PROBLEM IN ROUTING:

 The wXY-routing algorithm is designed to make meaningful routing

decisions whenever possible.
 However, in certain worst-case scenarios, routing problems can arise
which need to be dealt with.
 A livelock situation occurs when a packet is routed through a
network without ever reaching its destination.
 However, since the wXY-routing algorithm routes towards a
destination whenever possible, a livelock can only happen if a
packet is continuously misrouted away from its destination.
 This is a sign that there are no available routes to the destination.
 At this problem, the packet is removed from the network and a
feedback message is sent to the sender.
MICROARCHITECTURE OF wXY ROUTING
ALGORITHM
 MICROARCHITECTURE OF wXY ROUTING
ALGORITHM(CONT…)

 The microarchitecture of the wXY-routing and on-demand VCB

assignment components of the AdNoC router is illustrated .
 If the incoming flit is a header flit then the weight of a possible route
is calculated .
 The direction of the transaction is also stored in the LUT.
 All control bits of the route allocation stem from the header decoder
of the router.
 For following flits, the route allocation part decides based on the
LUT.
 In the right-bottom part of the figure, a crossbar to select an
appropriate VCB is implemented.
SIMULATION RESULT

Simulation results for packet hold

SIMULATION RESULT(cont..)

Simulation results for north

SIMULATION RESULT(cont..)

Simulation results for packet discard

 CONCLUSION

 It provides an adaptive route allocation algorithm to meet varying

bandwidth guarantees and an on-demand buffer block assignment
scheme for runtime connection establishment between a data
producer and a data consumer.

 Our proposed on-demand buffer assignment scheme increases the

on-chip resource utilization (buffer) and decreases the overall buffer
use, on an average, 42% in our case study analysis compared to a
static approach where a fixed number of buffer blocks is tied to the
output port.
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