M-RAM

Shashwat Shriparv
dwivedishashwat@gmail.com
InfinitySoft
Memory Category
 Volatile Memory Comparison
The primary difference between different memory types is the bit cell.


SRAM Cell

word lin
• Larger cell lower density, higher cost/bit
• Read non-destructive
• No refresh required
• Simple read  faster access
bit line bit line
•
• DRAM Cell
word line
•
• Smaller cell  higher density, lower cost/bit
• Needs periodic refresh, and refresh after read
• Complex read  longer access time
• bit line
 Limitation of Flash Memory
 The main weakness of flash memory is the number of
times that data can be written to it. Data can be read
from flash as many times as desired, but after a certain
number of "write" operations, it will fail. Most flash
devices are designed for about 100,000 - 1,000,000
write operations (or "write cycles").


 The erase command takes much longer than the write

process; and, for manufacturing reasons, flash memory
chips are not made with the ability to erase individual bits
or bytes. Only large sections of memory (usually 512
bytes or more) can be erased at a time.
 MRAM Introduction
• It is a non-volatile, random access memory
technology that is designed to initially
replace flash memory and, potentially,
DRAM memory.
• MRAM uses magnetic, thin film elements on
a silicon substrate that can be built on the
same chip with the logic circuits.

The MRAM product, called MR2A16A .
•
 MRAM - The “Universal” Memory
• MRAM is a revolutionary,
non-volatile memory chip with
potential to replace all other forms
of semiconductor memories
• Allows single memory solution for
multiple memory options within one
chip - enabling faster, lower power,
less expensive solutions for next-
generation wireless and portable
products
• MRAM offers solution to
technology shortcomings such as
slow computer or cell phone
startup, data loss, long waits for
data to load and short battery life
 Information flux.
Information Information Information
Information
transmission Processing storage
Input
word
Outside

Output

DRAM, MRAM Magnetic (HDD)

Optical (CD, DVD)
 MRAM Advantages
Nonvolatile Data Retention  10 years

Fast Symmetrical Read/Write

25-35ns for 4Mb at 0.18um technology node

Unlimited
Endurance (>1016 )
Cycles Data stored by magnetic polarization

Viable Integrated with Existing CMOS Baseline

Compatible with Embedded Designs

4Mb Memory Device sampled

 History and development...

M-RAM based on:

Ø M-RAM – quick view.
ØGMR effect - 1980th.
Ø Magnetoresistivity.
ØTMR effect – 1995 year.
•
• 1989 - IBM scientists made a string of key discoveries
about the "giant magnetoresistive effect" in thin-film
structures.
•
• 2000 - IBM and Infineon established a joint MRAM
development program.
•
• 2003 - A 128 kbit MRAM chip was introduced
•
• 2004 -Renesas Technology Develops High-Speed, High-
Reliability MRAM Technology.
•
• 2005 - Renesas Technology and Grandis to Collaborate
on Development of 65 nm MRAM Employing
Spin Torque Transfer.
 Behavior of a ferromagnet in a magnetic field

H
Ms H Ms

M N M
S N S

H H
S
N S N

Linear Hysteresis
response
 Memory !!
 Sensor !!
 Magnetic LEGO and Magnetoresistance

Stack of ferromagnetic thin layers Resistance can be used

separated by non-magnetic layers to determine the magnetic
state of stack
FM

FM VV

Normal metal Insulator

(Cu, Au) (Al2O3)
 Giant magnetoresistance (GMR)

Ferromagnetic Resistance depends

thin films (Co, on magnetic field
NiFe) separated
by thin non- RAP >> RP
magnetic metal
spacers
(Cu, Au)
spin-valve

multilayer

granular
system
 Two current model of GMR

Parallel state Anti-parallel state

Low resistance High resistance

Spin-down Spin-down
x
x x
Spin-up x Spin-up
Co Cu Co Co Cu Co

RMaj RMaj RMaj Rmin

Spin-down Spin-down

Spin-up Spin-up

Rmin Rmin Rmin RMaj

GMR =
(α -1) 2
α = Rmin /RMaj
4α
 Tunnel magnetoresistance (TMR)

Ferromagnet 1
Large effects at RT first observed
Ferromagnet 2 by Moodera et al. PRL 74, 3273
(1995)
AFM

Ultrathin insulator
Al2O3 ~ 1.0 nm

State-of-the-
art:
TMR of up to
70% at 300 K
 Storage and states of a bit.

MRAM: charge and spin.

Storage state:
Soft ferromagnet

charge of capacitor.„1”
Insulator
[%]

ØDRAM: Hard ferromagnet

ØFlash, EEPROM: charge on floating gate.

ØFeRAM: charge of a ferroelectric capacitor.

TMR

„0”
Field [Oe]
Magnetic Random Access Memory (MRAM)

Cross point
architecture

Magnetic memory
element

High resistance

Low resistance
Integration of MRAM (pizza style)

toppin
g

integration

Si
circuitry
crust
Writing a bit in MRAM

Send current
through metal word
and bit lines.

This creates a local

magnetic field to
switch a memory cell
at the cross point
 Reading a bit in MRAM

- Send current through element

- Measure its resistance (high or low)

But many parallel current paths

 diode or transistor needed
 Reading a bit in MRAM

Select one element in

array using isolation
transistor
p.s. Resistance
matching needed !

- Send current through a single element

- Measure its resistance (high or low)
 How MRAM Works
§Information is stored as magnetic polarization, not charge
§
§The state of the bit is detected as a change in resistance
§

Magnetic layer 1 (free layer)

S N N S
Tunnel barrier
S N S N
Magnetic layer 2 (fixed layer)
Magnetic vectors are parallel – Magnetic vectors are anti-parallel –
low resistance. “0” high resistance. “1”
• MRAM normally functions by
constructing minuscule magnetic
fields at intersections in a grid of
nanoscopic power rails. When
current attempts to travel through a
power rail which is opposing the
polarization of one of the magnetic
field bits, its current flow is mitigated
and the bit value stored by the field is
detected by this weakened current
flow.
 MRAM Cell

• Magnetoresistive random access

memory (MRAM) uses the magnetic Diode
tunnel junction (MTJ) to store
information Bit Line
• MRAM cell composed of a diode and an
MTJ stack
• MTJ stack consists of two ferromagnetic MTJ Stack Pt
Co/F
Read/Write Current Ni/F
e2O
layers separated by a thin dielectric Al
e
Co/F
barrier Ni/F
3
e
Mn/
e
Pt
Fe
• Polarization of one layer fixed, other W
used for information storage

•
•
Word Line
•
 1 T-1 MTJ MRAM memory cell operation - read

Read Mode
To read an MRAM bit,
current is passed through
ISense the bit and the resistance
of the bit is sensed.

Isolation
Transistor
“ON”
 1 T-1 MTJ MRAM memory cell operation - write

“Write Mode” To write an MRAM bit, current

Easy Axis Field is passed through the
programming lines generating
IEas magnetic fields.
Free Layer
y Tunnel Barrier The sum of the magnetic field
from both lines is needed to
Fixed Layer program the bit.
Hard Axis Field No moving parts.
IHard
Isolation
Transistor
“OFF”
 Other MRAM cell architectures.

Twin cell arrays:

ØCircuit is faster than the 1T1TMR implementation.
ØLess atractive on a cell density and cost basis.
Diode cell:
ØSOI diodes allow the integration of a memory with most
circuits without sacrificing silicon wafer surface area.
ØSOI diodes suitable for this aplication haven’t been
developed yet.
Transistorless array:
ØLarge reduce in cell area.
ØComplex circuity required to read bit state, slow read.
 4Mb Memory Cell
M5-BL i

TE
V4 TJ TVia
Program path MVia
M4-DL i BE
for Writing
V3
information
M3
V2 Sense Path for
M2 bit cell reading
Thk V1 Pass Xtor Pass Xtor Group Select
Oxide
M1
Xtor
N+ N+ N+ N+ N+ N+ N+
P-

Layer Name M1-3 Via1-4 M4-DL MVia BE TJ TVia TE M5-BL

 MRAM 32Kb
memory segment.
Bit Bit line
line 0 31
Digit
line
Word line

Word line
Digit
line
MRAM Reference Circuit
Bit Line

Rmax
Rmin
Word Line
common source

Word Line

Rmax Rmin

Rref = 1/2 * (Rmin + Rmax)

Reference Cell

Reference Cell uses Parallel/Serial combination of MTJ’s in

two memory states to generate “mid resistance” reference
between those two states
 Implementation
of 1-MTJ / 1-transistor cell.

NiFe (free layer)

Al2O3 (tunneling barrier)
CoFe (fixed layer)

SAF
Ru

CoFe (pinned layer)

Word
line
Toggle Bit Technology
 Full MTJ Stack for MRAM
Full MTJ Stack
for MRAM

Top electrode Low resistance contact

Switches between two magnetic states in applied field.

Free Stores information.
AlOx Tunnel barrier. Affects resistance and MR ratio.
Fixed Synthetic Antiferromagnet (SAF). AF coupling through Ru
Ru layer makes the structure stable in applied magnetic fields.
Pinned Relative thickness of Fixed and Pinned used to center loop.

AF pinning layer Pins the bottom magnetic layers.

Template
Seeds growth, determines crystal structure
Seed

Base electrode Low resistance contact

 Toggle MRAM Bit Cell
BL
Program
Program
Bit Line
Line
Line
2

Ferromagnetic layer
Free Tri-Layer Coupling Layer
Tunnel Barrier Ferromagnetic layer
Pinned Ferromagnetic
Pinning Layer
DL
Program
Program
Line
Line1
 Elements of Toggle Bit
Hard Easy
Axis Axis
• Balanced SAF
free-layer
• Bit oriented 45º to
lines Write
Line 1
(H1)
• Unipolar currents
• Overlapping
pulse sequence Write
Line 2
• Pre-read / (H2)

decision write
•
 Toggle MRAM Switching Sequence
H2 H2

Hard Easy Hard Easy Hard Easy Hard Easy Hard Easy
Axis Axis Axis Axis Axis I2 Axis Axis I2 Axis Axis Axis
H1 H1
I1 I1

Write Write Write Write Write

Line 1 Line 1 Line 1 Line 1 Line 1

Write Write Write Write Write

Line 2 Line 2 Line 2 Line 2 Line 2

On Write Line 1
Off

On
Write Line 2
Off
t0 t1 t2 t3 t4
 Sample Application – Battery Backed
SRAM Replacement
“Built-in-house” Components
•Problems
Addr/Dat
a Bus SRAM •System design complexity
•Board space and weight Addr/Dat
a Bus
MCU
MCU •Battery life
CE Contro Ba
l tte
ry
•Manufacturing complexity
Chip
•Environmental concerns MRAM
– •Solutions
•Single chip solution
•Problems •Simple, low cost system
•Cost design
Addr/Dat Battery
MCU
a Bus
•Manufacturing complexity •Manufacturing simplification
SRAM •No battery
•Battery life
•Low performance •Unlimited life
•Environmental concerns •Smaller profile
–
“Off-the-shelf” components •Higher performance
•Environmentally friendly
 Target Application – Battery
Backed SRAM Replacement
More Parts & Labor &
System Design Board Space & Weight
Complexity
• Primary Usage
– Data
Logging
– Parameter
Storage
– System
Status
– Storage
Buffers
•Battery Contact Failure Manufacturing
•Out-of-Tolerance Complexity
Voltage Spikes
•Limited Life
 MR2A16A Application Spaces
►Target Application
Spaces
–Data Streaming
•RAID systems
and servers
•POS terminals
•Data-acquisition
systems
•Data logging
•Buffers
•Routers / ►Currently not targeting high
switches
density, space-constrained
•Printers / copiers
–System Configurationapplications
•Black-box –Portable digital audio players
applications –Jump drives
•Gaming –Digital camera data storage
•System status –
MRAM parameters
 Major limitations of MRAM:


• Although MRAM has many advantages over virtually

every existing memory type, it is still in its infancy.
Many had hoped MRAM would usher in the age of
instant-on computers able to replace the computer
main memory and hard drives, but, due mainly to its
cost, these hopes remain a dream.
• At $25 per 0.5 MB, MRAM has no chance of competing
with existing RAM selling for $25 per 256 MB, not to
mention Flash, which sells for $25 per 1 GB.
• The only place where MRAM might be widely utilized is
in specialized markets, for example, as a Battery-
Backed SRAM replacement. Only when it breaks its
current high price per MB ratio will MRAM's unique
qualities find widespread usage.
 Roadmap to future
storage technologies.

RRAM
with
CMR
 Bio – MRAM,
vision for tomorrow?

MRAM Biomolecule labeled by magnetic markers

array
 MRAM Roadmap ?

Honeywell GMR-MRAM
limited performance

4 Motorola tunnel
MRAM demo’s
0.256
 Conclusion
• Non Volatile
• No need to refresh
• (potentially) High density
• Non destructive read
• Read speed = write speed; < 50ns
• Unlimited R/W endurance
• Soft error immunity
•
  Thank you

Shashwat Shriparv
dwivedishashwat@gmail.com
InfinitySoft