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Preparation For Midterm
Preparation For Midterm
Preparation For Midterm
• Hamming Code
RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Register Read Address
Memory Instr[20-16] Read Addr 2 Data 1 zero
Data
Read File
PC Instr[31-0] 0 ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1
Instr[31-26]
PC[31-28]
Shift 28
Instr[25-0]
left 2 2
0
1
Memory 0
PC
0 Read Addr 1
A
Address
IR
ALUout
Read Data
0 File
(Instr. or Data) ALU
Write Addr
1 Read
B
Write Data Data 2 0
1 Write Data
4
MDR
1
0 2
Instr[15-0] Sign Shift 3
Extend 32 left 2 ALU
Instr[5-0] control
Multiple Clock Cycle Finite State Machine
Comparing Single and Multiple Clock Machines
Generating the Next State Equations
PLA Implementation of Multi Clock PLA
PLA Implementation of Multi Clock FSM
Micro-Programmed Control
• Relatively Fast
Microinstruction Encoding: Indirect Encoding
Vertical Micro-programming
• Slower
Next Address Decision ?
• Like a normal computer, we want to allow
branches. Why?