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Interfacing of 8051: Unit 4
Interfacing of 8051: Unit 4
UNIT 4
Contents
• Interfacing of 7 segment display, LCD and
keyboard.
DP G F E D C B A NUMBER
0 0 0 0 0 1 1 0 1
0 1 0 1 1 0 1 1 2
0 1 0 0 1 1 1 1 3
PROGRAM 7 SEGMENT DISPLAY
• To display ‘1’
MOV A,#06H
MOV P1,A
SJMP $
LCD Interfacing
Pin No: Name Function
• To use the internal clock generator of the ADC804, the CLK IN and CLK R pins are
connected to a capacitor and a resistor. In that case, the clock frequency is
determined by the equation.
f = 1/1.1RC
R=10K and C=150pF f=606Hz
the conversion time is 110us.
Input Voltage range of ADC
Vref/2 Vin
Step size (mV)
(Volts) (Volts)
0.5 0 to 1 1/256=3.90
• Default 0-5V. Can be changed by setting
different value for Vref/2 pin.
Vin=Vin(+) – Vin (-)
• Range = 0 to 2x Vref/2.
for Vin = 2x Vref/2. we get 256 as a digital
output on D0-D7
• Step Size a Smallest change
– (2 x Vref/2)/ 256 for ADC804
for eg for step size 10mv ,digital output on
D0-D7 changes by one count for every 10mv
change of the input analog voltage.
Algorithm
• Make CS=0 and send a low-to-high to pin
WR to start the conversion.
• Keep monitoring INTR
– If INTR =0, the conversion is finished and we
can go to the next step.
– If INTR=1, keep polling until it goes low.
• After INTR=0, we make CS=0 and send a
high-to-low pulse to RD to get the data out of
the ADC804 chip.
ADC Interfacing
ADC_IO:
mov P1, #0xff ; To configure as input
setb p3.4
clr p3.7 ;Chip select
AGAIN
setb P3.6 ;RD=1
clr P3.5 ;WR=0
setb P3.5 ;WR=1- low to high transition
WAIT:
jb P3.4, WAIT ;wait for INTR
clr P3.6 ;RD=0 -High to low transition
mov A, P1 ;read digital o/p
sjmp AGAIN
DAC Interfacing
• Iout= Iref (D7/2+D6/4+D5/8+D4/16+D3/32+D2/64+D1/128+D0/256)
• Vout=Iout x R
Interfacing of Relay with 8051
Interfacing LDR with 8051