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Fundamental of Computer Architecture: November 01, 2003
Fundamental of Computer Architecture: November 01, 2003
Fundamental of Computer
Architecture
ROM
RAM
I/O
Address bus
C ontrol bus
Instruction Cycle
R 0
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 8
M
1 0 0 0 0
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 9
Terminology
◆ IR : Instruction Register
◆ MAR : Memory Address
Register
◆ LOAD R0,[10000]
◆ LOAD R1,[10001]
◆ ADD R2, R0, R1
◆ LOAD R0,[10002]
◆ ADD R1, R0,R2
◆ STORE [10003],R1
◆ LOAD R0,[10000]
◆ LOAD R1,[10001] M
◆ ADD R0,R1
◆ LOAD R2,[10002]
◆ ADD R0,R2
◆ STORE [10003],R0
◆ LOAD [10000]
◆ ADD [10001]
◆ ADD [10002]
◆ STORE [10003]
◆ A,B, C,….
◆ SP
◆ Accumulator
LOC35003:
LOAD R1,#14999
LOAD R3,#10000
LOAD R2,[R3]
Me
ADD R0, R2
INC R3
DEC R1
Branch_NZ
LOC35003
STORE [R3],R0
◆ Relative X[PC]
◆ Index
Bef
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 26
Direct addressing
◆ LOAD R1,[1200H]
Be
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 27
Register indirect
◆ load R0,[R1]
Bef
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 28
Index addressing
◆ Use index register
◆ Effective address = X + [Ri]
◆ When X = offset (or displacement)
◆ Ri = index register or Base register
STRT: LD R0,#1000H
LD R1,#2000H
LD R3,#1024
LOC_A: LD R4, [R0]
STORE [R1], R4
INC R0
INC R1
DEC R3
BRANCH>0 LOC_A
CALL PRINTF
◆ Multiply
8-bit unsigned number
◆C = A * B
◆ Control Unit
MAR <= PC
ADDRESS_BUS <= MAR,
Read
MDR <= MAR <= PC, Read, Z <= PC+4 , MDR <= MEMORY[MAR]
MEMORY[MAR], WMFC PC <= Z, WMFC
IR <= MDR
IR <= MDR
Z <=
PC + 4
PC <= Z
b u s B
C o n s t a n t 4
M U X
Data bus
Instruction Decoder
Control Unit and B A
incrementer
R(n-1)
A L U
MDR
PC
R1
R0
Address bus
IR
:
MAR
. . . .
c o n t r o l s i g n a l s
b u s C
Step Action
◆ 1 PCout, R=B, MARin, Read, incPC
◆ 2 WMFC, MDRin_from_databus
◆ 3 MDRout_busB, R= B, IRin
◆ 4 R4out_busB, R5out_busA, Add, R6in,
End
◆ Microprogrammed
E x t e r n a l I
D e c o d e r /
I R
E n c o d e r
C o n d i t i o n
C o n t r o l s i g n a l s
240-208 Fundamental of Computer Architecture Chapter 3 - The Processing Unit 48
Control Unit organization
C o n t r o l S t e p
C lo c k
C o u n t e r
S t e p d e c o d e r
T1
T2
Tn
I N S 1
I N S 2 E x t e r n a l I n p
I N S 3
I n s t r u c t io n
I R E n c o d e r
D e c o d e r
C o n d i t i o n c o
I N S m
R u n E n d
A d d
T 4 Z i n
B R
T 1
N
E n d
B R N
T 4
A d d
T 7
C lo c k u P C
C o n t r o l s t o r e C o n t r o l W