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Challenges of CMOS Technology - Farhana
Challenges of CMOS Technology - Farhana
Figure Main challenges for CMOS technology at the 21-nm technology node.
(YI SONG et al., 2011). Mobility Enhancement Technology for Scaling of CMOS
Devices: Overview and Status.
1. Carrier-Transport of CMOS using New Channel
Materials and Structures
nMOSFET pMOSFET
Channel direction - <100> on (100) surface
<110> on (110) surface
Surface orientation (100) (110)
Strain in Si/Ge bi- or uni-axial tensile bi-axial tensile uni-axial
compressive
Materials III-V SiGe/Ge
Table ways to enhance carrier transport properties in MOS channels.
(Takagia et al., 2007). Carrier-Transport-Enhanced CMOS using New Channel
Materials and Structures.
A) Challenges for III-V CMOS
Advantages:
i. Best hole mobility (unlike III-V)
ii. Si(Ge) already used in logic technology
iii. Col-IV: Non-Polar
Challenges:
Reference device is highly strained silicon
• To take full advantage of electron and hole mobility, nMOS devices should be fabricated on
Si(100) and pMOS devices on Si(110).
Litho OPC (optical proximity correction) has now been applied for several
node generations & design optimization of other process areas such as RIE,
RTA, CMP and epitaxial film growth are increasingly
used in recent generations.
4. Multi‐Gate Fin Transistor
Multi-Gate Transistors have better SCE:
– Gates reduce spread of Vdrain Enables lower threshold voltage
– Enable lower channel doping ( ↑μ)
Ultimate transistors may need tunnel injection at ultra-low Vcc. Would need new materials with
more efficient tunneling and atomic scale fabrication control
Band‐to‐Band Tunneling (BTBT) Transistor suffer from extremely poor drive current
Need materials with more efficient tunneling