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Watchdog
Watchdog
Prescaler divider PR[2:0] bits Min timeout (ms) Max timeout (ms)
RL[11:0]= 0x000 RL[11:0]= 0xFFF
4 000 0.125 512
8 001 0.25 1024
16 010 0.5 2048
32 011 1 4096
64 100 2 8192
128 101 4 16384
256 110 8 32768
256 111 8 32768
Window watchdog (WWDG) features
• prescaled from the APB1 clock
• has a configurable time-window that can be programmed to detect abnormally late or early
application behavior.
• Used to detect software fault which cause program to abandon its normal sequence.
• generates an MCU reset during downcounter value is below 0x40, unless the program refresh
the downcounter value before the downcounter value go below 0x40.
• Also generate MCU reset when downcounter value is refreshed by software before the
downcounter has reached the window register value.
• It is a programmable free running downcounter. (activate through software)
• Include an interrupt called Early wakeup interrupt (EWI), triggered when the downcounter is
equal to 0x40. (can be disabled)
• WWDG enabled by setting the WDGA(activation bit) in the WWDG_CR register, then it cannot be
disabled again except by a reset.
WWDG use free running downcounter, counting down even if the
watchdog is disabled. When the watchdog is enabled, the T6 bit (avoid
value that below 0x40) must be set to prevent generating an immediate
reset.
• T[5:0] bits contain the number of increments which represents the time delay before the watchdog
produces a reset.
• Configuration register (WWDG_CFR) contains the high limit of the window (window register value).
• To avoid reset, the downcounter must reload when downcounter have the value between 0x3F and window
register value.
• Program still can perform software reset by setting WDGA=1 and T6=0.
Advanced watchdog interrupt feature
• Early Wakeup Interrupt (EWI) can be used if specific safety operation
need to performed before the actual reset is generated.
• It is enabled by setting the EWI bit in the WWDG_CFR register.
• When the downcounter reaches the value 0x40, an EWI interrupt is
generated (interrupt service routine) can be used to trigger specific
actions before resetting the device.
• Interrupt service routine (ISR) and (EWI) can actually reload the
WWDG counter T[6:0] to avoid the WWDG reset, then trigger some
required actions.
• The EWI interrupt is cleared by writing '0' to the (EWIF) bit in the
WWDG_SR register. This bit is set by hardware when the counter has
reached the value 0x40.