 Circuits for counting events are

frequently used in computers and other

digital systems.
 Since a counter circuit must remember its
past states, it has to possess memory.
 The number of flip-flops used and how
they are connected determine the
number of states and the sequence of the
states that the counter goes through in
each complete cycle.
 Counters are divided in two categories,
these are:
• Asynchronous (Ripple) Counters - the first flip-
flop is clocked by the external clock pulse, and
then each successive flip-flop is clocked by the
Q or Q' output of the previous flip-flop.
• Synchronous Counters - all memory elements
are simultaneously triggered by the same clock.
 DECADE COUNTER
 UP-DOWN COUNTER
 ODD –EVEN COUNTER
 JOHNSON COUNTER
 DECADE COUNTER
 UP-DOWN COUNTER
 ODD –EVEN COUNTER
 RING COUNTER
 A ripple UP counter is an asynchronous counter where only
the first flip-flop is clocked by an external clock. All
subsequent flip-flops are clocked by the output of the
preceding flip-flop. Asynchronous counters are also called
ripple-counters because of the way the clock pulse ripples
it way through the flip-flops.
 The MOD of the ripple counter or asynchronous counter is
2n if n flip-flops are used. For a 4-bit counter, the range of the
count is 0000 to 1111 (24-1). A counter may count up or count
down or count up and down depending on the input control.
The count sequence usually repeats itself. When counting
up, the count sequence goes from 0000, 0001, 0010, ... 1110 ,
1111 , 0000, 0001, ... etc.
 A ripple counter is an asynchronous counter where
only the first flip-flop is clocked by an external clock.
All subsequent flip-flops are clocked by the output of
the preceding flip-flop. Asynchronous counters are
also called ripple-counters because of the way the
clock pulse ripples it way through the flip-flops.
 The MOD of the ripple counter or asynchronous
counter is 2n if n flip-flops are used. For a 4-bit
counter, the range of the count is 0000 to 1111 (24-1). .
The count sequence usually repeats itself.
 When counting down the count sequence goes in the
opposite manner: 1111, 1110, ... 0010, 0001, 0000,
1111, 1110, ... etc.
• It counts up or down depending on the
status of the control signals UP and
DOWN.
• When the UP input is at 1 and the DOWN
input is at 0, the NAND network between
FF0 and FF1 will gate the non-inverted
output (Q) of FF0 into the clock input of
FF1.
• Similarly, Q of FF1 will be gated through
the other NAND network into the clock
input of FF2.
• Thus the counter will count up.
 Once the counter counts to ten (1010),
all the flip-flops are being cleared.
 Notice that only Q1 and Q3 are used to
decode the count of ten.
 This is called partial decoding, as
none of the other states (zero to nine)
have both Q1 and Q3 HIGH at the same
time.
A ring counter is a type of counter
composed of flip-flops connected into
a shift register, with the output of the last
flip-flop fed to the input of the first,
making a "circular" or "ring" structure.
 Johnson counter also known as creeping counter,
is an example of synchronous counter. In Johnson
counter, the complemented output of last flip flop
is connected to input of first flip flop and to
implement n-bit Johnson counter we require n
flip-flop.It is one of the most important type of
shift register counter. It is formed by the
feedback of the output to its own input .Johnson
counter is a ring with an inversion .Another name
of Johnson counter are creeping counter, twisted
ring counter, walking counter, mobile counter
and switch tail counter.
 The shift register, which allows serial input
and produces serial output is known as
Serial In – Serial Out (SISO) shift register.
 In this shift register, we can send the bits
serially from the input of left most D flip-
flop. Hence, this input is also called
as serial input. For every positive edge
triggering of clock signal, the data shifts
from one stage to the next. So, we can
receive the bits serially from the output of
right most D flip-flop. Hence, this output is
also called as serial output.
 The shift register, which allows serial input
and produces parallel output is known as
Serial In – Parallel Out (SIPO) shift register
 In this shift register, we can send the bits
serially from the input of left most D flip-
flop. Hence, this input is also called
as serial input. For every positive edge
triggering of clock signal, the data shifts
from one stage to the next. In this case, we
can access the outputs of each D flip-flop in
parallel. So, we will get parallel
outputs from this shift register.
 The shift register, which allows parallel
input and produces serial output is known
as Parallel In − Serial Out (PISO) shift
register
 In this shift register, we can apply
the parallel inputs to each D flip-flop by
making Preset Enable to 1. For every
positive edge triggering of clock signal, the
data shifts from one stage to the next. So, we
will get the serial outputfrom the right most
D flip-flop.