SRI VENKATESWARA COLLEGE OF ENGINEERING AND

TECHNOLOGY (AUTONOMOUS)
(Approved by AICTE, New Delhi, Affiliated to JNTUA, Anantapuram,
Accredited by NAAC & NBA , Bengaluru)
R.V.S.Nagar, Chittoor, Andhra Pradesh – 517127

A Project Review
on
Design of Configurable multipliers by using dual quality
of 4:2 compressors
PRESENTED BY SUPERVISOR
T.N.KAVYA (14781A04L9) Mr.M.RAJESH
. PUSA SWATHI (14781A04G9) ASSISTANT PROFESSOR
P.KUJA (14781A04F6) ECE
N.DIMPUL REDDY (14781A04E3)
CONTENTS
 Abstract
 Introduction

 Existing system

 Disadvantages

 Proposed system

 Extension work

 Advantages

 Applications

 Tools
ABSTRACT
 Multiplier plays a vital role in many applications such as digital image
processing, digital signal processing etc so it is important to design the
multiplier with low power consumption and reduced delay.
 In order to reduce this factor we design the multiplier using four 4:2
compressor and these compressors has a switching mode and this is used to
switch between the exact and approximate modes
 During approximate and exact mode each of these compressors has different
power consumption and delays but only at approximate mode these
compressors has its own level of accuracy.
 The efficiencies of these compressors in a 32-bit Dadda multiplier are
evaluated and by comparing their parameters with those of the state-of-the-art
approximate multipliers
INTRODUCTION
 Many scientific and engineering problems are computed using accurate,
precise and deterministic algorithms.
 the lack of approximate techniques targeting the partial product generation,
we introduce the partial product perforation method for creating approximate
multipliers.
 We omit the generation of some partial products, thus reducing the number of
partial products that have to be accumulated; we decrease the area, power,
and depth of the accumulation tree. By reducing the quality (accuracy), the
delay and/or power consumption of the unit may be reduced.
HALF ADDER

Half Adder is digital circuit which performs addition of two bits. A Half adder takes in
two inputs 'A' and 'B'. It gives two outputs 'Sum' and 'Carry'. The overflow in case of a
multi digit addition is indicated by the 'Carry' signal

Figure . Half Adder

FULL ADDER

Full adder takes in three inputs 'A', 'B', 'C' and gives two outputs 'Sum' and 'Carry'. Normally the
third input is often termed as 'Cin' to indicate it as a carry from the previous addition stage.
EXISTING SYSTEM
 The conventional 4-2 compressor structure actually compresses five partial product bits into
three . The architecture can be implemented with two stages of full adder (FA) connected in
series as shown in Fig.1 The outputs of 4-2 compressor consist of one bit in position j and
two bits in position (j + 1). This straight forward approach has four XOR gate delays.
EXISTING SYSTEM
ARRAY MULTIPLIER

8X8 Array Multiplier

 In an array multiplier, multiplication is based on shift and add. The partial
product is generated by the multiplication of the multiplicand with one
multiplier bit.
 The partial product are shifted according to their bit orders and then added
with carry propagate adder. Array multiplier is easy to design due to its
regular structure .
 However, the main disadvantage of the array multiplier is that as the width of
the multiplier increase the delay becomes more. This is because the worstcase
delay of the multiplier proportional to the width of the multiplier.
DISADVANTAGES

 Delay increased
 Power consumption increased
 The uneven delay profile of the outputs arriving from different input paths
tends to generate a lot of glitches.
 PROPOSED SYSTEM
 We present four dual-quality reconfigurable approximate 4:2 compressors,
which provide the ability of switching between the exact and approximate
operating modes during the runtime.
 The basic structures of the proposed compressors consist of two parts of
approximate and supplementary.
 In the approximate mode, only the approximate part is active whereas in the
exact operating mode, the supplementary part along with some components
of the approximate part is invoked.
Figure 2 :Block diagram of the proposed approximate 4:2
compressors
BLOCK DIAGRAM

Figure : Block diagram of proposed system

EXACT 4:2 COMPRESSOR

 exact 4:2 compressor is composed of two serially connected full adders

In this structure, the weights of all the inputs and the sum output are the same whereas the weights of
the carry and Cout outputs are one binary bit position higher.
 The outputs sum, carry, and Cout are obtained from
DQ4:2C1 (DUAL QUALITY 4:2 COMPRESSOR1)

Fig. (a) Approximate part and (b) overall structure of DQ4:2C1.

 The approximate output carry (i.e., carry) is directly connected to the input x4
(carry = x4), and also, the approximate output sum (i.e., sum) is directly
connected to input x1 (sum = x1).
 In the approximate part of this structure, the output Cout is ignored. While the
approximate part of this structure is considerably fast and low power, its error rate
is large.
 The supplementary part of this structure is an exact 4:2 compressor.

 In the exact operating mode, the delay of this structure is about the same as that of
the exact 4:2 compressor.
DQ4:2C2 (DUAL QUALITY 4:2 COMPRESSOR2)

Fig. (a) Approximate part and (b) overall structure of DQ4:2C2.

 In the first structure, while ignoring Cout simplified the internal structure of the
reduction stage of the multiplication, its error was large. In the second structure,
compared with the DQ4:2C1, the output Cout is generated by connecting it
directly to the input x3 in the approximate part.

 While the error rate of this structure is the same as that of DQ4:2C1, its relative
error is lower.
DQ4:2C3 (DUAL QUALITY 4:2 COMPRESSOR3)

Fig. (a) Approximate part of DQ4:2C3 and (b) overall structure of DQ4:2C3.
 The previous structures, in the approximate operating mode, had maximum power
and delay reductions compared with those of the exact compressor.
 In some applications, however, a higher accuracy may be needed. In the third
structure, the accuracy of the approximate operating mode is improved by
increasing the complexity of the approximate part.
 the utilized NAND gate of the approximate part (denoted by a blue dotted line
rectangle) is not used during the exact operating mode. Hence, during this
operating mode, we suggest disconnecting supply voltage of this gate by using the
power gating.
DQ4:2C4 (DUAL QUALITY 4:2 COMPRESSOR4)

Fig. (a) Approximate part of DQ4:2C4 and (b) overall structure of DQ4:2C4.
 In this structure, we improve the accuracy of the output carry compared with that
of DQ4:2C3 at the cost of larger delay and power consumption where the error
rate is reduced.
 The supplementary part is indicated by red dashed line rectangular while the gates
of the approximate part, powered OFF during the exact operating mode, are
indicated by the blue dotted line.
 the error rate corresponds to the occurrence of the errors in the output for the
complete range of the input.
ACCURACY METRICS

Pass Rate: It is the number of correct by the total number of outputs

.
ADVANTAGES
 Less delay
 Low power consumption
APPLICATIONS
 Digital signal processing
 Image processing
TOOLS
 Xilinx 14.3 for synthesis and simulation results
 Verilog HDL coding language
 RESULTS

Block diagram:
RTL SCHEMATIC
Technology schematic:
Simulation results
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