Verilog Hardware Description

Language
LECTUER-1

DIVYA SHAH
24/02/09
 WHY VERILOG
• TO DESCRIBE DIGITAL CIRCUITS

• GENERAL PURPOSE HARDWARE DESCRIPTION LANGUAGE

• SIMILAR IN SYNTAX TO C PROGRAMMI9NG LANGUAGE

• DIFFERENT LEVEL OF ABSTRACTION MIXED IN THE SAME

MODEL(FROM BEHAVIORAL,DATAFLOW TO SWITCH LEVEL)

 DESIGN METHODOLOGIES
• TOP-DOWN DESIGN
DEFINE TOP LEVEL BLOCKS AND IDENTIFY THE SUB-BLOCKS
NECESSARY TO BUILD THE TOP LEVEL BLOCK.FURTER SUBDIVIDE
THE SUB-BLOCKS UNTIL GET THE LEAF-CELL BLOCKS WHICH CANT
BE DIVIDE FURTHER.

• BOTTOM-UP DESIGN
FIRST IDENTIFY THE BUILDING BLOCKS THAT ARE AVAILABLE .
THEN BUILD BIGGER CELL.THUS THESE CELLS USED FOR HIGHER
LEVEL BLOCKS UNTIL WE BUILD TOP LEVEL BLOCK IN DESIGN
 MODULE

• In Verilog, the basic unit of hardware

is called a module.
• Modules cannot contain definitions of
other modules.
• A module can, however, be instantiated
within another module.
• Allows the creation of a hierarchy in a
Verilog description
 MODULE DECLARATION

• module module_name (port

list);
• <Port declarations>;
• <module internals>;
• endmodule
 LEVELS OF ABSTRACTION
• BEHAVIORAL OR ALGORITHMIC LEVEL:
Highest level of abstraction
No need to concern for the hardware implementation detail
Designing is very similar to c programming language

• DATAFLOW LEVEL:
Specify the flow of data
Designer has to concern how the data flow occur b/w hardware
register & how the data is procecssed in the design

• GATE LEVEL:
Implemented in terms of logic gates and interconnection b/w these
gates
Designing is same as describe a design in terms of gate level logic
diagram
• SWITCH LEVEL:
Lowest level of abstraction
Implemented in terms of switches,storage nodes and interconnection
b/w them

IMP:
• Designer can mix and match all levels of abstraction
(e.g RTL: behavioral+dataflow)
• Higher level of abstraction flexible and technology independent
design
• Lower level of abstraction inflexible and technology dependent
design
 INSTANCES
• THE PROCESS OF CREATING OBJECTS FROM A
MODULE TEMPLATE IS CALLED “INSTANTIATION”
AND THE OBJECTS ARE CALLED “INSTANCES”.

• Example:
A 4-bit full adder is shown to you .it instantiates 4 one bit full adder
and again one bit full adder instantiates 2 xor,3 and & 2 or gates.
 Instantiating the module
Example: 4-bit full adder circuit

In2[2] In1[2] In2[1] In1[1] In2[0] In1[0] cin

In2[3] In1[3]

FA0
FA2 FA1
FA3

c1 c0
c2
Sum[1] Sum[0]
Cout Sum[3] Sum[2]
module fadd4(in1, in2, cin, sum,cout);
input[3:0] in1,in2;
input cin;
output[3:0] sum;
output cout;
wire[2:0] temp_cout;

fadd(in1[0],in2[0],cin,sum[0],temp_cout[0]);
fadd(in1[1],in2[1],temp_cout[0],sum[1],temp_cout[1]);
fadd(in1[2],in2[2],temp_cout[1],sum[2],temp_cout[2]);
fadd(in1[3],in2[3],temp_cout[2],sum[3],cout);
endmodule
 Structural model of a full adder circuit
module fadd(in1, in2, cin, sum,cout);
input in1,in2, cin;
output sum, cout;
wire x1,a1,a2,a3,o1,o2;

xor(x1,in1,in2);
xor(sum,x1,cin);
and(a1,in1,in2);
and(a2,in1,cin);
and(a3,in2,cin);
or(o1, a1,a2);
or(cout,o1,a3);
endmodule
 STIMULAS BLOCK
• A Verilog procedural block which
executes only once.
• Used for simulation.
• Stimulas block also called testbench.
• Testbench generates clock, reset, and
the required test vectors.
• Two style of stimulas application
 FIRST STYLE
HERE STIMULAS BLOCK INSTANTIATES THE DESIGN BLOCK AND
DIRECTLY DRIVE THE SIGNALS IN THE DESIGN BLOCK

CLK RESET

DESIGN BLOCK

Q
 SECOND STYLE
• HERE STIMULAS AND DESIGN BLOCK BOTH ARE INSTANTIATES IN A
TOP LEVEL DUMMY MODULE.HERE STIMULAS BLOCK INTERACTS
WITH THE DESIGN BLOCK ONLY THROUGH THE INTERFACE.

D_CLK CLK

RESET
STIMULAS D_RESET DESIGN
BLOCK D_Q Q BLOCK