CMOS Analog Design Using

All-Region MOSFET Modeling

Chapter 2
Advanced MOS transistor modeling

CMOS Analog Design Using All-Region MOSFET 1

Modeling
Semiconductors
 Four types of charge are present inside a
semiconductor: the fixed positive charge of ionized
donors, the fixed negative charge of ionized
acceptors, the positive mobile charge of holes, and
the negative mobile charge of electrons.
 We consider all donors and acceptors ionized
 
ND  N D and N A  N A

 On this basis, the net positive charge density ρ is

  q ( N D  N A  p  n)

CMOS Analog Design Using All-Region MOSFET 2

Modeling
Boltzmann’s Law – (1)
 In equilibrium electrons and holes follow Boltzmann’s
law and their concentrations (number per unit
volume) are proportional to
-( Energy / kT )
 e
 k=1.38x10-23 J/K - Boltzmann constant
 T - absolute temperature (K).
 electron and hole densities in equilibrium are related
to electrostatic potential  by
q ( 1 2 )
p( 1) 
e kT
p( 2)
 q=1.6x10-19 C
CMOS Analog Design Using All-Region MOSFET 3
Modeling
 Boltzmann’s Law – (2)
 n0 and p0 - equilibrium electron and hole concentrations
in the neutral bulk (=0 )
q q

p  p0e kT
 p0e u
n  n0e kT
 n0eu

u   / t - normalized electrostatic potential

t  kT / q - thermal voltage
 the mass-action law is
np  ni2

ni - concentration of electrons (and holes) in the intrinsic

semiconductor
CMOS Analog Design Using All-Region MOSFET 4
Modeling
Example: Calculate the built-in potential for a Si p-n
junction with NA = 1017 atoms/cm3 and ND = 1018
atoms/cm3 ,T=300K
In equilibrium, if we choose the potential origin  = 0 where the
semiconductor is intrinsic (i.e., where p0=n0=ni), then

p0  ni e  / t
n0  ni e / t
 / t
Far from the junction in the n-side n0  N D  ni e nregion
p region / t
Far from the junction in the p-side p0  N A  ni e
The built-in potential is given by

 ND    NA   ND N A 
bi  n  region   p  region  t ln     t ln     t ln  2 
 ni    i 
n  i 
n
bi  26  ln 1015   900 mV

CMOS Analog Design Using All-Region MOSFET 5

Modeling
The two-terminal MOS structure

CMOS Analog Design Using All-Region MOSFET 6

Modeling
 The ideal two-terminal MOS structure
(VFB=0) A
VG
Cox  ox
tox
A - capacitor area,
Q QG M tox - oxide thickness
VG  s  G
Cox ox - permittivity of oxide
O
+ QC S
QG Cox  ox
s QG  
; Cox  
A A tox
_
QC
QG  QC  0 VG  s 
Cox

CMOS Analog Design Using All-Region MOSFET 7

Modeling
Example: oxide capacitance
(a) Calculate the oxide capacitance per unit area for tox=
5 and 20 nm assuming ox = 3.90, where 0= 8.85·10-14
F/cm is the permittivity of free space. (b) Determine the
area of a 1pF metal-oxide-metal capacitor for the two
oxide thicknesses given in (a).

Answer: (a) =690 nF/cm2 = 6.9 fF/m2 for tox=5 nm and =

172 nF/cm2= 1.7 fF/m2 for tox= 20 nm. The capacitor
areas are 145 and 580 m2 for oxide thicknesses of 5
and 20 nm, respectively.

CMOS Analog Design Using All-Region MOSFET 8

Modeling
The flat-band voltage
In equilibrium (with the two terminals shortened/open), the
contact potential between the gate and the semiconductor
substrate of the MOS induces charges in the gate and the
semiconductor for VGB=0.
Charges inside the insulator and at the semiconductor-insulator
interface also induce a semiconductor charge at zero bias.

The effect of the contact potential and oxide charges can be

counterbalanced by applying a gate-bulk voltage called the
flat-band voltage VFB.

QC
VG  VFB  s 

Cox
CMOS Analog Design Using All-Region MOSFET 9
Modeling
 Example: flat-band voltage
(a) Determine the expression for the flat-band voltage of n+
polysilicon-gate on p-type silicon (b) Calculate the flat-band voltage
for an n+ polysilicon-gate on p-type silicon structure with NA = 1017
atoms/cm3.
Answer: (a) In equilibrium, by analogy with an n+ p junction, the
potential of the n+-region is positive with respect to that of the p-
region. The flat-band condition is obtained by applying a negative
potential to the n+ gate with respect to the p-type semiconductor of
value
 NA 
VFB _ n  p  bi _ n  p  0.56 V  t ln  
 ni 
(b)
VFB  0.56 V  t ln 107   980 mV

CMOS Analog Design Using All-Region MOSFET 10

Modeling
Regions of operation of the MOSFET:
Accumulation (p-substrate)

G VGB  VFB
QG QC  0
- - - - - - - - - - -
Qo
s  0
+ + + +
VGB ++++++++++++++
QC Holes + accumulate in
the p-type semiconductor
surface

CMOS Analog Design Using All-Region MOSFET 11

Modeling
Regions of operation of the MOSFET:
Depletion (p-substrate)
VGB  VFB
G QC  0
QG
+ + + + + + + + +
0  s   F
Qo Holes evacuate from the P
- -- - - -Q - -- -
+ + + +
VGB semiconductor surface and
- - - -
C
acceptor ion charges -
become uncovered

B F = Fermi potential ( to be defined)

CMOS Analog Design Using All-Region MOSFET 12

Modeling
Regions of operation of the MOSFET:
Inversion (p-substrate)

G
VGB  VFB
QG QC  0
s   F
+ + + + + + + + +
Qo

- -- - ---Q - -- -
+ + + +
VGB
electrons approach the
-- -- - - - - -
C
surface!
- - -
B

CMOS Analog Design Using All-Region MOSFET 13

Modeling
 Inversion for p-type substrate
Volume charge density inside the semiconductor:
  q( p0e  n0e  n0  p0 )
u u

Depletion of holes prevails over electron charge when

u
p0 e  n0 e or, equivalently
u

t p0 tp02 p0
  ln( ) mass-action
 ln( 2 )  t ln( )  F
2 n0 law 2 ni ni

For  >F the concentration of minority carriers (n)

becomes higher than that of majority carriers (p); the
semiconductor operates in the inversion region
CMOS Analog Design Using All-Region MOSFET 14
Modeling
 Small-signal equivalent circuit of the
MOS capacitor  dQC 1
dQG dQC  
C gb 
 
Cgb  dQ  d 1
dVG dVG d s  C  s 
Cox dQC Cox
1
 
Cgb
1 1

Cc Cox
Cc   dQC ds

d  QB  QI 
Cc    Cb  Ci
ds

CMOS Analog Design Using All-Region MOSFET 15

Modeling
 Main approximation for compact MOS
modeling: the charge-sheet model
Minority carriers occupy a zero-thickness layer at the Si-SiO2
interface, where   s

s /t dQI QI

QI  e Ci   
d s t
Charge-sheet + depletion approximation for the bulk charge gives

QB  qN A xd   2q s N A s  t 

2q s N A  Cox   2q s N A / Cox

Cb  
2 s  t 2 s  t is the body-effect coefficient

CMOS Analog Design Using All-Region MOSFET 16

Modeling
The three-terminal MOS structure
VG
VC Carrier concentrations in Si
substrate follow Boltzmann’s
n+ p law:
n, p  exp(-Energy/kT)

The origin of potential  is taken deep in the bulk

q q ( VC )

p  p0 e kT
 p0e u ; n  n0e kT
 n0eu uC
electrons are no longer in equilibrium with holes due to the bias of
the source-bulk junction VC

pn  ni2e uC  ni2e VC / t

CMOS Analog Design Using All-Region MOSFET 17
Modeling
 Small-signal equivalent circuit of the 3-
terminal MOS device
dQI  Cb  Cox  Ci

dVC Ci  Cb  Cox

 1 1
dQI     dVC
 Cox  Cb Ci 
Approximations:

1) depletion capacitance per unit area is constant along the

channel and is calculated neglecting inversion charge

2) Charge sheet model Ci  QI / t

CMOS Analog Design Using All-Region MOSFET 18

Modeling
The linearization surface potential sa
Determination of sa  s Q 0 VG
Cox
I
QI  0
_
Potential balance +
s  sa
QB Ci  0 _
VG  VFB  sa   sa   sa  t

Cox Cb QB
+

2  dsa Cox 1
sa  t  VG  VFB  t    
4 2 dVG Cox  Cb n

CMOS Analog Design Using All-Region MOSFET 19

Modeling
 Example: slope factor
For tox = 5 nm and 20 nm determine the minimum doping NA for
which the slope factor n < 1.25 at sa = 2F.
Answer: For sa=2F

Cb 2q s N A 2q s N A

n =1+  1  1
Cox  sa
2Cox  2F
2Cox

 0.25 2F 4Cox2

2
Thus, for n=1.25
NA=
2q s
where F is a weak (logarithmic) function of NA. Using 2F = 0.8 V
for the first calculation, we obtain after two iterations that NA>
4.9x1015 atoms/cm3 for tox=5nm, and NA > 2.3·1014 atoms/cm3 for
tox=20 nm.

CMOS Analog Design Using All-Region MOSFET 20

Modeling
 The Unified Charge Control Model
(UCCM) - 1

 1 1

dQI     dVC
 
 Cox  Cb Ci 

Approximations:
1) depletion capacitance per unit area is constant along the
channel and is calculated neglecting inversion charge
2) Charge sheet model Ci  QI / t

CMOS Analog Design Using All-Region MOSFET 21

Modeling
 The Unified Charge Control Model
(UCCM) - 2
 1 1
dQI     dVC  1 t 
 Cox  Cb Ci  dQI     dVC
 nCox QI 
Ci  QI / t
Cb
where n  1   n VGB 

Cox
Integrating from an arbitrary channel potential VC to a reference
potential VP yields the unified charge control model (UCCM)

 QIP
  QI  QI  
VP  VC  t   ln     QI V
QIP
 nCox t  
 QIP
C VP

CMOS Analog Design Using All-Region MOSFET 22

Modeling
 The “regional” strong and weak
inversion approximations
 QIP
  QI  QI 
VP  VC  t   ln  
 nCox t 
 QIP 

VP  VC t VP  VC t
strong inversion weak inversion
  QI  
QI  nCox VP  VC  VP  VC  t ln    1

  QIP  
or, equivalently
VP VC t
t
QI  QIP
e

CMOS Analog Design Using All-Region MOSFET 23

Modeling
Example : approximate UCCM
(a) Calculate the value of the inversion charge density, normalized
to nCox t , for which the value of the voltage VP-VS
calculated using the SI approximation differs from that
calculated using UCCM by 10 %; (b) Same using the WI
approximation ; (c) comment on ‘moderate’ inversion (MI)

Answer: a) qI  (VP  VC ) / t

SI approximation error of less than 10 % for q’I > 20
VP VC t
t
b) WI approximation qI  e
WI approximation error of less than 10 % for q’I < 0.22.
(c) MI region : SI and WI approximations give errors greater than
10 % for the control voltage VP-VS. The inversion charge
density variation from the lower to the upper limit of the MI
region is approximately two orders of magnitude (20/0.22).

CMOS Analog Design Using All-Region MOSFET 24

Modeling
The pinch-off charge density
The channel charge density corresponding to the effective
channel capacitance times the thermal voltage, or thermal
charge, defines pinch-off

  Cb )t  nCox

  (Cox
QIP  t

The name pinch-off is retained herein for historical reasons

and means the channel potential corresponding to a small
(but well-defined) amount of carriers in the channel.

CMOS Analog Design Using All-Region MOSFET 25

Modeling
 The pinch-off voltage VP
The channel-to-substrate voltage (VC) for which the channel
charge density equals is called the pinch-off voltage VP.

QI  Cbt e sa F C  t  Cox (n  1)t e sa F C  t

in weak   2 V /   2 V /
inversion

UCCM is
  n 
asymptotically correct VP  sa  2F  t 1  ln  
in weak inversion if   n  1 

VP  sa  2F

CMOS Analog Design Using All-Region MOSFET 26

Modeling
Threshold voltage
Equilibrium threshold voltage VT0, for VC=0:
Gate voltage for which QI  QIP  t
  nCox
or
Gate voltage for which VP=0

VP  sa  2F
Recalling that
VG  VFB  sa   Cox sa  t

it follows that VT 0  VFB  2F   2F

CMOS Analog Design Using All-Region MOSFET 27

Modeling
 Example: threshold voltage
+
Estimate VT0 for an n-channel transistor with n polysilicon gate,
NA=1017 atoms/cm3 and tox=5 nm.
Answer: The flat-band voltage (slide 10) is -0.98 V; F=0.419; C’ox=
690 nF/cm2. The body-effect factor is   2q s N A / Cox  0.264 V

VT 0  VFB  2F   2F =  0.98  0.838  0.264 0.838= 0.1V

For this low value of the threshold voltage, the off-current (for VGS=0)
is too high for digital circuits.
Solution to control the magnitude of the threshold voltage without an
exaggerated increase in the slope factor a non-uniform
high-low channel doping.

CMOS Analog Design Using All-Region MOSFET 28

Modeling
 Pinch-off voltage vs. gate voltage
4.0
4.00E+00 2

2.0

3.00E+00
3.0
1.5
1.5
pinch-off voltage

slope factor
2.00E+00
2.0
1
1.0
1.00E+00
1.0

0.5
VP
0.5

0.00E+00 0 dVP dsa Cox 1

  
 
dVG dVG Cb  Cox n
-1.0
-1.00E+00 0 0
0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00

0 1.0 2.0 3.0 4.0 5.0 VG (V)

VT0 (equilibrium threshold voltage)
VGB  VT0
Useful approximation: VP 
n
CMOS Analog Design Using All-Region MOSFET 29
Modeling
The MOS transistor

W xi xi

I D     J n dxdz  W  J n dx
0 0 0

CMOS Analog Design Using All-Region MOSFET 30

Modeling
‘Exact’ I-V model of the MOSFET (1)
 d  dn
J n  qn  n     qDn
 dy  dy VS  VC  VD
drift diffusion

q ( VC )
dn n  d dVC 
n  n0 e kT
 n0e u uC    
dy t  dy dy 
Using the Einstein relationship Dn  nt

d  d dVC  dVC
J n  qn  n  qn  n     qn  n
dy  dy dy  dy

CMOS Analog Design Using All-Region MOSFET 31

Modeling
‘Exact’ I-V model of the MOSFET (2)
W xi xi

I D     J n dxdz  W  J n dx dVC
xi

0 0 0 I D  qW  nn dx
dVC dy
J n  qn  n
0
xi
dy QI  q  ndx
0

dVC
I D  W  nQI
dy
Since the current is constant along the channel

nW VD
ID    QI dVC L is the channel length
L VS

CMOS Analog Design Using All-Region MOSFET 32

Modeling
Charge-sheet formula for the current

QI VG
Ci  
t
dQI  Ci  dVC  ds 

dV C d s dQI dVC
+ _
dVC  ds  t J n  qn  n
dQI QI dy

ds dQI
I D  I drift  I diff   nWQI  nW t
dy dy

CMOS Analog Design Using All-Region MOSFET 33

Modeling
 Charge control compact model (1)
VG ds dQI
I D   nWQI  nW t
dQI dy dy
Cox
dVC + _
d s   Cb )ds  nCox
dQI  (Cox  ds
Ci _
dQB
Cb +
nW dQI
ID   (QI  t nCox
 )

nCox dy
Integrating along the channel yields

nW  QIS
 2  QID
 2 
ID    t  QIS  
  QID
L  
2nCox 

CMOS Analog Design Using All-Region MOSFET 34

Modeling
 Charge control compact model (2)
drift + diffusion

 nW  QIS
 2  QID
 2   Q  QID
   Q  QID
 
ID    t  QIS      nW  IS
  QID  t   IS
 nCox 
L  
2nCox   2   nC 
ox L 

dQI  nCox
 ds
“virtual” charge

  QID
 QIS    s 0  sL 
I D   nW  
 nCoxt   
 2  L 

average average
charge density electric field

CMOS Analog Design Using All-Region MOSFET 35

Modeling
Charge control compact model (3)
To emphasize the symmetry of the rectangular geometry
MOSFET

ID  IF  IR

W  Q  2 
I F ( R)  n 
IS ( D )
 ( D) 
 t QIS
L  2nCox  

(compare with Ebers-Moll model of the BJT)

CMOS Analog Design Using All-Region MOSFET 36

Modeling
Drain current vs. gate-to-bulk voltage

CMOS Analog Design Using All-Region MOSFET 37

Modeling
Comparing UCCM and the surface potential
model with exact numerical solution of
Poisson equation

CMOS Analog Design Using All-Region MOSFET 38

Modeling
 Modeling the bulk charge from
accumulation to inversion
  s  t (es / t  1)
Charge-sheet approximation QB   sgn(s )Cox

Potential balance VG  VFB  s   QI  QB  / Cox

sa  s Q  0
I

VG  VFB  sa 2   2 sa  t e  sa t

1 

n  1
1 dQB
 1
Cb
 1

sgn sa   1  e sa / t 
Cox ds s sa
Cox 
2 sa  t e sa t  1 

CMOS Analog Design Using All-Region MOSFET 39

Modeling
Modeling from accumulation to inversion:
Surface potential and pinch-off voltage (VP)

CMOS Analog Design Using All-Region MOSFET 40

Modeling
 Transistor symmetry
1. I D  I D VG ,VS ,VD  VG

Voltages referenced to local substrate: VS VD

VG VGB VS VSB VD VDB B ID

2. Symmetry
B
I D VG ,V1,V2   I D VG ,V2 ,V1  V1 ID V2

VG

CMOS Analog Design Using All-Region MOSFET 41

Modeling
Normalization
3. For a long-channel MOSFET
W
I D  I F  I R  I S i f  ir   I SQ  f VG ,VS   f VG ,VD  
L
I F  R   I S  qIS  D  2  2qIS  D   D
ID
qIS  D   QIS  D  /  nCox t 
i f r   I F  R / I S
t2 WW
G IF  IR
I S  Cox n  I SQ B
2 L L

IS and ISQ are the normalization (specific)

current and the “sheet” normalization S
current, slightly dependent on bias.

CMOS Analog Design Using All-Region MOSFET 42

Modeling
Forward and reverse currents
Long-channel MOSFET I D  I F  I R  I (VG ,VS )  I (VG ,VD )
IF: forward current IR: reverse current

IR=
IF=

CMOS Analog Design Using All-Region MOSFET 43

Modeling
Specific current t2 W W
The specific (normalization) current I S  Cox n  I SQ
2 L L
ISQ : process parameter slightly dependent on VG and T
ISQ 25 nA (p-channel)
ISQ 75 nA (n-channel)
in 0.35 m CMOS

CMOS Analog Design Using All-Region MOSFET 44

Modeling
Pinch-off voltage and slope factor (1)
UCCM VP  VS ( D )  t  qIS  ( D ) 
 ( D )  1  ln qIS & qIS ( D )  1  i f ( r )  1
2
 
2
 
 
VP   VG  VT 0   2F      2F
  2 2
 
Linearization:
VG  VG 0
VP  VP 0 
VP Slope =1 Slope =1/n n VG 0 

n VG 0   1 
2 VP 0  2F
VP0 In particular:
VG  VT 0
VP 
n VT 0 

VT0 VG0 VG n VT 0   1 
2 2F

CMOS Analog Design Using All-Region MOSFET 45

Modeling
Pinch-off voltage and slope factor (2)

Determination of the pinch-off voltage and the slope factor as

functions of VG. NMOS transistor W=20 m, L=2 m, 0.18 m
CMOS technology.

CMOS Analog Design Using All-Region MOSFET 46

Modeling
The I-V relationship (1)
VP  VS  t  1  i f  2  ln
  
1  i f 1 

1,00E-03
10-3 VD = VG
ID (A)
1,00E-04
VD
VS = 0 V
ID
1,00E-05

0.5
1.0
10-6
1,00E-06
1.5
2.0 VG VS
1,00E-07

2.5

1,00E-08 3.0

10 -9
1,00E-09
0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00 4,50E+00
0 1 2 3 4 VG (V)
Common-source characteristics
CMOS Analog Design Using All-Region MOSFET 47
Modeling
The I-V relationship (2)
VP  VS  t  1  i f  2  ln
  
1  i f (r ) 1 

10-3
ID (A) VD = VG
VG = 4.8 V
VD
ID
10-6

VG
0.8 V VS

10-9
0 1 2 3 VS (V)

Common-gate characteristics VG=0.8, 1.2, 1.6,

2.0, 2.4, 3.0, 3.6, 4.2, and 4.8 V
CMOS Analog Design Using All-Region MOSFET 48
Modeling
Weak inversion model
VG  VT 0
 
Weak inversion
 VS ( D )  t  1  i f ( r )  2  ln 1  i f (r )  1 
if(r)<1 n  
-1 if(r)/2
 VG VT 0 
 VS  / t W
I D  I 0e
 n  1  eVDS / t  I0   n   t2e1  2 I S e1
nCox
  L

CMOS Analog Design Using All-Region MOSFET 49

Modeling
Strong inversion model (1)
VG  VT 0
n
 VS ( D )  t  1  i f ( r )  2  ln
  
1  i f (r )  1 


Strong inversion VG  VT 0
 VS ( D )  t i f ( r )  t I F ( R ) I S
if(r)>>1 n

W  2
  G T0 S  G T0 D
2
I D  I F  I R   nCox V  V  nV  V  V  nV
2nL  

Moderate inversion
1<if(r) <100 Both sqrt(.) and ln(.) terms are important

CMOS Analog Design Using All-Region MOSFET 50

Modeling
Strong inversion model (2)
ID
VDS

VG
ID/IF

VDSsat=VP=(VG-VT0)/n VDS

Transistor output characteristic

CMOS Analog Design Using All-Region MOSFET 51

Modeling
Strong inversion model (3)
Cox W Cox W
ID ID  VG  VT 0  ID ID  VG  VT 0  nVS 
2n L 2n L

SCE, , n,
“model”
VT0
VDD
VG VG  VT 0  n VS
ID VDD
ID

VG
VG
VS

CMOS Analog Design Using All-Region MOSFET 52

Modeling
 Universal output characteristics
VDS  qIS   1  i f 1 
 qIS  qID
  ln    1  i f  1  ir  ln  

t  
 qID  1  ir  1 

(o): measured
(—): model

(a) if= 4.5x 10-2 (VG=0.7 V); (b) if= 65(VG= 1.2 V); (c) if= 9.5x102 (VG= 2.0 V); (d) if=
3.1x 103 (VG= 2.8 V); (e) if= 6.8x 103 (VG= 3.6 V); (f) if= 1.2x 104 (VG= 4.4 V).
CMOS Analog Design Using All-Region MOSFET 53
Modeling
Saturation voltage
 / qIS  
Saturation voltage (VDSsat) – VDS such that qID

VDSsat  t ln 1    1   
  1  i f 1 
  1   is the saturation level

CMOS Analog Design Using All-Region MOSFET 54

Modeling
Transconductances - 1
Transconductances I D  g mg VG  g ms VS  g md VD  g mb VB

I D I I I
g mg  g ms  g md  g mb  0 g mg  , g ms   D , g md  D , g mb  D
VG VS VD VB

  IF  IR   IF W
Calculation of gms g ms       QIS
 VS  VS L

W
g md 
   QID
L Pao-Sah ID (UCCM)
(i f  ir )
g mg  I S
VG i f i f g ms  g md
 g mg 
UCCM
VG nVS n
ir i g
 ms
 r g mg in saturation
VG nVD n
CMOS Analog Design Using All-Region MOSFET 55
Modeling
Transconductances - 2

VDD
ID

VG
VS

Source transconductance VG= 0.8, 1.2, 1.6, 2.0, 2.4, 3.0, 3.6,
4.2, and 4.8 V (W=L=25 m, tox=280 Å)

CMOS Analog Design Using All-Region MOSFET 56

Modeling
 Transconductances - 3

VDD
ID

VG VS

Gate transconductance VS= 0, 0.5, 1.0,1.5, 2.0, 2.5, and 3.0 V .

W=L=25 m, tox=280 Å
CMOS Analog Design Using All-Region MOSFET 57
Modeling
The transconductance-to-current ratio - 1
g ms ( d )t 2 1 WI (if <1)
Transconductance  2
-to-current ratio I F (R) 1  i f (r )  1  SI (if >>1)
i f (r )
102

gms/IF

W=25 m
tox = 28 nm (IS = 26 nA)
Seqüência1
101 L=25 m, tox= 280 Å
tox = 5.5 nm (IS = 111 nA)
Seqüência2

L=20 m, tox= 55 Å

model
Seqüência3

100
1,00E-03 1,00E-01
10-4 10-2 100 102 if 104

CMOS Analog Design Using All-Region MOSFET 58

Modeling
The transconductance-to-current ratio - 2
Transconductance g ms ( d )t 2 1 WI (if <1)

-to-current ratio I F (R) 1  i f (r )  1 2
 SI (if >>1)
i f (r )
2
1,00E+02
10
gms/IF

V GB = 1.0 V (IS = 33 nA)

Seqüência1 W=L=25 m, tox= 280 Å
1
1,00E+01
10 VGB = 2.0 V (IS = 26 nA)
Seqüência2

VGB = 3.0 V (IS = 24 nA)

Seqüência3

model
Seqüência4

0
1,00E+00
10 1,00E-04
10 -4 1,00E-03 1,00E-02
10 -2 1,00E-01 1,00E+00
10 0 1,00E+01 1,00E+02
10 2 if
1,00E+03 1,00E+04
10 4

CMOS Analog Design Using All-Region MOSFET 59

Modeling
The transconductance-to-current ratio - 3
Transconductance g ms ( d )t 2 1 WI (if <1)

-to-current ratio I F (R) 1  i f (r )  1 2
 SI (if >>1)
i f (r )
101002
gms/IF

10101 L = 25 m (IS = 26 nA)

Seqüência1
W=25 m, tox= 280 Å
L = 2.5 m (IS = 260 nA)
Seqüência2

model
Seqüência3

0
101,00E-04
1
1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01 1,00E+02 1,00E+03 1,00E+04 1,00E+05
10-4 10-2 100 102 if 104

CMOS Analog Design Using All-Region MOSFET 60

Modeling
The low-frequency small-signal model
G

g md v d

id
g mb vb
S D

g ms v s

g mg v g
B

CMOS Analog Design Using All-Region MOSFET 61

Modeling
Quasi-static charge-conserving model
 The current entering each terminal of the transistor is split into
a transport component (IT) and a capacitive charging term.

dQD W VD t 
I D (t )  IT (t )  I T (t )  n  QI (VC )dVC
dt L VS t 

 Quasi-static approximation: To calculate the stored charges

we suppose that the charge stored in the transistor depends
only on the instantaneous terminal voltages
Neglecting leakage currents
L
QG  W  QG dy I G (t ) 
dQG
0 dt
L dQB
QB  W  QB dy I B (t ) 
0
dt
CMOS Analog Design Using All-Region MOSFET 62
Modeling
Ward-Dutton partition of the channel
charge
L y L
y
QS  W  (1  )QI dy QD  W  QI dy
0 L 0 L

dQS dQD
I S (t )  IT (t )  I D (t )  IT (t ) 
dt dt
dQD dQS dQI
As expected I D (t )  I S (t )   
dt dt dt

L
QI  W  QI dy is the total inversion charge stored
0
in the channel

CMOS Analog Design Using All-Region MOSFET 63

Modeling
 Calculation of stored charge - 1

I D  I drift  I diff 
ds dQI
  nWQI   nW t
dy dy nW
dy   '  QI  nCox
 t  dQI
dQI  nCox
 ds nCox I D

It is convenient to define QIt  QI  nCox

 t

nW
dy   '
QIt dQIt
nCox ID

CMOS Analog Design Using All-Region MOSFET 64

Modeling
 Calculation of stored charge - 2
L
QI  W  QI dy
nW 2 QF 
  ox t  It
0
QI   Q   nC   Q  dQ 
It 
nW   QR It
I D nCox 
dy   '
QIt dQIt
nCox ID
nW 2  QR3  QF3 QR2  QF2 
QF ( R )  QIS  t
 ( D )  nCox QI     t
 nCox 
 ID 
nCox 3 2 
nt (W / L)
Using ID  QF2  QR2  we find that
 
 2nCox t 
2

 2 QF2  QF QR  QR2  In weak inversion

Q I  WL   nCoxt 
   QID
(QIS  )
 3 Q 
F  Q R  QI  WL
or 2

2  QIS
2 3(QIS  QID
  QID
2 )  nCox
 t (QIS
  QID
 ) In strong inversion &
QI  WL saturation
  QID
QIS   2nCox  t
QI   2 3WLQIS

CMOS Analog Design Using All-Region MOSFET 65
Modeling
Total inversion, source and drain charges
=1 in WI
Channel linearity   nCox
QR QID  t
 
coefficient QF QIS
  nCox
 t 0 in SI sat

=1 in SI for VDS=0

 2 1    2 
QI  WL    nCox
(QIS  t )  nCox
 t 
 3 1  
 6  12  8 2  4 3 n 
QS  WL    nCox
(QIS  t )  Cox
 t 
15 1   
2
 2 

 4  8  12 2  6 3 n 
QD  WL    nCox
(QIS  t )  Cox
 t 
15 1   
2
 2 

CMOS Analog Design Using All-Region MOSFET 66

Modeling
Capacitive coefficients - 1
Using the quasi-static approximation
dQ j Q j dVG Q j dVS Q j dVD Q j dVB
   
dt VG dt VS dt VD dt VB dt

 Qj  Qj
Defining C jk   jk C jj 
 Vk 0 Vj
0

 dQ G / dt   C gg  C gs C gd C gb   dVG / dt 
    
dQ
 S / dt  C C  C  C  SdV / dt
sg ss sd sb 
 dQ / dt   C dg C ds C dd C db   dVD / dt 
 D
  
 dV / dt 
 dQ / dt   C 
 B   bg C bs C bd C bb   B 

CMOS Analog Design Using All-Region MOSFET 67

Modeling
Capacitive coefficients - 2
 The 16 capacitive coefficients are not linearly
independent
Assume VG  t   VS  t   VD  t   VB t   V (t )
Under equal terminal voltage variations, the charging
currents are zero. For the gate charging current, e.g.,
we have
dQG dV Cgg  Cgs  Cgd  Cgb
 (Cgg  Cgs  Cgd  Cgb ) 0
dt dt
Css  Csg  Csd  Csb
Similarly, for S, D, and B nodes Cdd  Cdg  Cds  Cdb
Cbb  Cbg  Cbs  Cbd

CMOS Analog Design Using All-Region MOSFET 68

Modeling
Capacitive coefficients - 3
Assume that d QG dVG d Q S dV
 Cgg ,  Csg G ,
dVS dVD dVB dt dt dt dt
  0 dQD dVG d Q B dV
dt dt dt  Cdg ,  Cbg G
dt dt dt dt

The sum of all the charging currents is

d QG d Q S d Q D d Q B dVG
    (Cgg  Csg  Cdg  Cbg )
dt dt dt dt dt
Charge conservation,
d(QS+QD+QB+QG)/dt=0 Cgg  Csg  Cdg  Cbg

CMOS Analog Design Using All-Region MOSFET 69

Modeling
Capacitive coefficients - 4
 Linear relationships between capacitive
coefficients

Cgg  Cgs  Cgd  Cgb  Csg  Cdg  Cbg

Css  Csg  Csd  Csb  Cgs  Cds  Cbs
Cdd  Cdg  Cds  Cdb  Cgd  Csd  Cbd
Cbb  Cbg  Cbs  Cbd  Cgb  Csb  Cdb

 Only nine out of the sixteen capacitive

coefficients are linearly independent
CMOS Analog Design Using All-Region MOSFET 70
Modeling
A complete set of 9 capacitive coefficients
for the MOSFET
2 1  2 qIS Cbs ( d )  (n  1)C gs ( d )
Cgs  Cox
3 1  1  qIS
2

2  2
 2 qID n 1
Cgd  Cox Cgb  Cgb  (Cox  Cgs  Cgd )
3   1  qID
1 
2 n

4   3 2   3 qID
Csd   nCox
15 1  1  qID
3

4 1  3   2 qIS
Cds   nCox
15 1  1  qIS
3

Cdg  Cgd  Cm  (Csd  Cds ) / n

CMOS Analog Design Using All-Region MOSFET 71

Modeling
Simplified small-signal MOSFET model
G

dvDB
g md vDB  Csd
Cgs
dt Cg
d
S Cgb
D
dv
g mg vGB  Cm GB
dt
Cbs Cbd

dvSB
g ms vSB  Cds
dt
B

CMOS Analog Design Using All-Region MOSFET 72

Modeling
The five capacitances of the simplified
model

Intrinsic capacitances simulated from (___) the charge-based and (o) from
the S- model (NMOS transistor, tox= 250Å, NA=2x1016 cm-3, and VT0=0.7V.
CMOS Analog Design Using All-Region MOSFET 73
Modeling
Capacitances of extrinsic transistor - 1

CMOS Analog Design Using All-Region MOSFET 74

Modeling
Capacitances of extrinsic transistor - 2

CMOS Analog Design Using All-Region MOSFET 75

Modeling
Non-quasi-static (NQS) small-signal
model
Channel segmentation: representation of the MOSFET
as a series combination of short transistors

CMOS Analog Design Using All-Region MOSFET 76

Modeling
Simplified high-frequency MOSFET model

C gd
g md vd
C gs 1  j  1   3 
1  j 1
1  j  1   2 
S
D Cgb
g mg vg  Cgb
1  j  1   4 
Cbs 1  j 1
1  j 1   2  Cbd
g ms vs 1  j 1   3 
1  j 1
B

CMOS Analog Design Using All-Region MOSFET 77

Modeling
Time constants of the NQS MOSFET
model

 4 1  3   2
1 
1  qIS 15 1   3
L2

t
 1 2  8  5 2
2 
1  qIS 15 (1   )2 (1  2 )

 1 5  8  2 2
3 
1  qIS 15 (1   ) 2(2   )

CMOS Analog Design Using All-Region MOSFET 78

Modeling
Quasi-static small-signal model

1<<1 2(3)<<1 non-quasi-static model

reduces to the five-capacitor model
G
g md vDB

C gs C gd
g mg vGB
S D Cgb
Cbs g ms vSB
Cbd

CMOS Analog Design Using All-Region MOSFET 79

Modeling
Example: Small-signal parameters
Calculate ID, VDSsat and small-signal parameters of a saturated n-
channel MOSFET in 0.35 m technology at if = 3 with
VSB= 0. W=10 m, L=1 m, tox=7 nm, n=1.2, n=400 cm2/V-s at 300 K.
Answer:
Cox =493 nF/cm2 and I SH  nCox nt2 / 2= 80 nA.
gmd = 0, Cgd = 0 and Cbd = 0 since the transistor is saturated.
I D  I F  (W / L) I SH i f  10  80  3  2.4 μA
 
VDSsat  t 3  1  i f  26(3  2)  130 mV

QIS
qIS    1 i f 1  1 3 1  1
 t
nCox
2  10  80 nA
g mg  (2 I S / nt )  1 i f 1  g mg 
1.2  0.026 V
 51 μA/V

CMOS Analog Design Using All-Region MOSFET 80

Modeling
Example: Small-signal parameters (continued)

2 1  2 qIS n 1
Cgs  Cox C gb  (Cox  C gs  C gd )
3 1  1  qIS
2
n
qID  1 1
  =1/(1+1)=0.5
qIS  1 qIS  1
  49 fF
Cox  WLCox
2 11 1
Cgs  49  14.5 fF
3 10.5 1  1
2

0.2
Cgb  (49  14.5  0)  5.75 fF
1.2

CMOS Analog Design Using All-Region MOSFET 81

Modeling
Intrinsic transition frequency

g mg g ms
fT  

2 C gs  C gb  
2 n C gs  C gb 
t
fT 
2 L 2
2 1  i f 1  
CMOS Analog Design Using All-Region MOSFET 82
Modeling
Example: Transition frequency
Determine the inversion level for which the transition
frequency of a minimum (nominal) length NMOS
transistor in the 0.35 m technology is 10 GHz at room
Answer:
Assuming that n=1.2 and n = 400 cm2/V-s at 300 K
it follows that

 
2
i f  1   L fT / nt
2
 1  21

Thus, operation in moderate inversion can be

considered for a design at 1 GHz, for example.

CMOS Analog Design Using All-Region MOSFET 83

Modeling
Main short-channel effects

 Mobility dependence on the electric field

 Channel length modulation
 Drain-induced barrier lowering
 Velocity saturation

CMOS Analog Design Using All-Region MOSFET 84

Modeling
Mobility dependence on the electric field
Inclusion of mobility variations in compact modeling: the constant
mobility is substituted with an effective mobility, which depends
on the applied voltages.
0
eff 
 QBS
  QIS QBD
  QID 
1     
 2 s 2 s 
0, the low-field mobility and , the scattering constant, are fitting
parameters
Another simplification: the effective transversal field is assumed
constant along the channel and equal to its value at pinch-off.
0
eff 

QBa
1  
s
CMOS Analog Design Using All-Region MOSFET 85
Modeling
 Channel length modulation
The dependence of the effective channel length on the drain-to-source
voltage is referred to as the channel length modulation (CLM).

S D
ID
 VDS  VDSsat 
L  LC ln 1   VDSsat
 V p 

VDS

L
0 Le L y
1    2
qIS  qID
ID  IS
L 1    qIS  qID
 
 qIS  
  qID
1
L
CMOS Analog Design Using All-Region MOSFET 86
Modeling
Drain-induced barrier lowering (DIBL)
 An increase in the drain voltage produces an increase in the
surface potential in the channel and, consequently, a reduction
in the potential barrier seen by the electrons at the source (
DIBL).

 The inclusion of the DIBL effect in MOSFET models is generally

through the threshold voltage.

  L 
VT  VT ,lc 
6t ox
2bi  VBS   VDS exp   
d1   4d 1  

VT  VT ,lc   bi  VSB   bi  VDB 

CMOS Analog Design Using All-Region MOSFET 87

Modeling
Velocity saturation effects - 1

s s dS
    F (longitudinal field)
F  s d S dy
1 1 Allows analytical
FC vsat dy
integration for ID
v
vsat

vsat
 FC
s s

FC F

CMOS Analog Design Using All-Region MOSFET 88

Modeling
Velocity saturation effects - 2
dQI  nCox ds

dVC s dQI  1 t  dVC

I D   WQI   
dy s dQI 
1 dy  nCox QI  dy
nCox vsat dy

 sWQI dQI  1 t 
ID    
1 dQI dy  ox
nC  Q 
I 
1
 FC dy
nCox
 sW 1   QID  
  QIS 
ID     QIP   QID
  
  QIS
 L
nCox Q  QIS
  2 
1  ID

LFC nCox

CMOS Analog Design Using All-Region MOSFET 89

Modeling
Velocity saturation effects - 3
   2
qIS  qID
Normalized current vs. iD   qIS  
  qID
normalized charge densities 1    qIS  qID
 

qI  QI /  nCox t  iD  I D / I S


 st / L 
vsat
W t2

I S   s nCox Normalization (specific) current
L 2

 short-channel parameter : ratio of diffusion-related

velocity to saturation velocity

CMOS Analog Design Using All-Region MOSFET 90

Modeling
Velocity saturation effects - 4
Saturation: The minimum amount of electron charge flowing at
the saturation velocity, required to sustain the current is


QIDSAT   I D / Wvsat 
2
qIS  1  qIDsat  1  qIDsat

S ID
D
QIS QI


QID

VDS

QIDSAT

0
CMOS Analog Design Using All-Region MOSFET 91
Modeling
Velocity saturation effects - 5
2
qIS  1  qIDsat  1  qIDsat
QIDSAT QIS 

1
Short channel

strong Long channel

weak
inversion inversion
 st L
vsat

10-2 100 102 104

 QIS nCox  t

CMOS Analog Design Using All-Region MOSFET 92

Modeling
Small dimension effects on charges
and capacitances

dVC s dQI  1 t  dVC

I D   WQI   
dy s dQI 
1 dy  nCox QI  dy
nCox vsat dy

sW  ID 
dy    
 QI  nCoxt   dQI
 ID 
nCox Wvsat 

CMOS Analog Design Using All-Region MOSFET 93

Modeling
Virtual charge formalism - 1

Virtual inversion charge density

ID
 t 
QV  QI  nCox
Wvsat

inversion +pinch off -saturation charge

densities

Along the channel dQV  dQI

sW  ID  sW
dy    
 QI  nCoxt  
 dQI   QV dQV
 ID 
nCox Wvsat   ID
nCox

CMOS Analog Design Using All-Region MOSFET 94

Modeling
Virtual charge formalism -2

sW dQV d s
ID   QV   sWQV

nCox dy dy

The drift of the virtual charge produces the

same current as the actual movement of
the real charge, which includes drift,
diffusion and velocity saturation

CMOS Analog Design Using All-Region

All Region MOSFET 95
Modeling
Channel linearity coefficient  with vsat
dQV
 sW
The integration of I D   QV from

nCox dy

source to drain results in

2  QVD
 sW QVS 2
ID 
 L
Cox 2n
 I D0 1   2 

QVD   nCox
QID   t  I D Wvsat
where  

QVS   nCox
QIS   t  I D Wvsat

CMOS Analog Design Using All-Region MOSFET 96

Modeling
Stored charges including vsat
The stored charge

QI  W 0LL QI dy  W LQIDsat



is calculated changing the integration variable

from y to QV
 sW
dy   QV dQV
 ID
nCox
resulting in
 2 1    2  LI D
Q I  W ( L  L)    nCox
QVS  t 
 3 1   vsat

CMOS Analog Design Using All-Region MOSFET 97

Modeling
Source and drain charges including vsat

CMOS Analog Design Using All-Region MOSFET 98

Modeling
Capacitive coefficients including vsat - 1
Le g ms 1 
2
2 1  2 qIS

Cgs  WLeCox 
3 (1   )2 1  qIS 3nvsat 1  2

Le g md 1 
2
2  2  2 qID
Cgd 
 WLeCox 
3 (1   )2 1  qID 3nvsat 1  2

n 1  Le gmg 1  
2
Cgb  Cbg   Cox  Cgso  Cgdo  
n  3vsat 1  2
 
4
Cds   nCoxW e L
2
1  3   2
q 
IS

1 g ms L
2
e  3  7 1  2

15 L 1 3 1  qIS 30 vsat L 1 3

1 g md L e2  3 7 1 
2
4 L e   3  
2 2 3
qID
Csd   nCox W 
15 L 1 3 1  qID 30 vsat L  
1
3

Cbs(d )   n 1 Cgs(d ) Cdg  Cgd   Csd  Cds  / n

CMOS Analog Design Using All-Region MOSFET 99

Modeling
Capacitive coefficients including vsat - 1

Normalized capacitances versus drain-source voltage

CMOS Analog Design Using All-Region MOSFET 100
Modeling
Gate-to-bulk capacitance with and
without the effect of velocity saturation

CMOS Analog Design Using All-Region MOSFET 101

Modeling