Professional Documents
Culture Documents
Instruction Set of 8085 Microprocessor By, Er. Swapnil V. Kaware
Instruction Set of 8085 Microprocessor By, Er. Swapnil V. Kaware
Microprocessor
For More Contents, do subscribe to
my channel on you tube as,
”Tech_Guru Swapnil Kaware”
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
Instruction Set of 8085
Microprocessor
Presented By,
Er. Swapnil V. Kaware,
svkaware@yahoo.co.in,
B.E.(Electronics), M.E. (Electronics)
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
What is Instruction ?????
• An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.
A 20 B MOV B,A A 20 B 20
A F A F
B 30 C B 30 C
D E
MOV M,B D E
H 20 L 50 H 20 L 50 30
A F A F
B C B C 40
D E
MOV C,M
D E
H 20 L 50 40 H 20 L 50 40
(2) Data Transfer Instructions
• MVI R, Data(8-bit)
• MVI M, Data(8-bit)
A F A F
B C B 60 C
D E
MVI B,60H D E
H L H L
204FH 204FH
40
HL=2050H HL=2050H
MVI M,40H
2051H 2051H
A A 30
30 LDA 2000H 30
2000H 2000H
• Example: LDAX D
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
A F A 80 F
B C 80 B C 80
2030H 2030H
LDAX D
D 20 E 30 D 20 E 30
A 50 A 50
50
2000H STA 2000H 2000H
• Example: STAX B
A 50 F A 50 F
B 10 C 20 B 10 C 20 50
1020H 1020H
D E
STAX B D E
H 30 L 60 H 30 L 60
60
204FH 204FH
30
2500H SHLD 2500H 2500H
2502H 2502H
• XCHG
• Example: XCHG
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
D 20 E 40 D 70 E 80
H 70 L 80 XCHG H 20 L 40
• SPHL
• Example: SPHL
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION
SP
H 25 L 00
SPHL
AFTER EXECUTION
SP 2500
H 25 L 00
• Example: XTHL
SP 2700 50 SP 2700 40
2700H 2700H
H L H L
30 40 60 60 50 30
2701H 2701H
XTHL
2702H 2702H
• PCHL
• Example: PCHL
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
PC PC 6000
H
60
L
00
PCHL H
60
L
00
• Example: IN 80 H
PORT 80H 10 A
IN 80H
AFTER EXECUTION
PORT 80H 10 A 10
• Example: OUT 50 H
PORT 50H 10 A 40
OUT 50H
AFTER EXECUTION
PORT 50H 40 A 40
• Addition
• Subtraction
• Increment
• Decrement
• ADD R
• ADD M
• The contents of register or memory are added to
the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair.
A 20 A 50
B C 30 B C 30
D E ADD C D E
H L
H L
A=A+R
A 20 ADD M A 30
B C B C
D E
A=A+M D E
H 20 L 50 10 H 20 L 50 10
2050 2050
(2) Arithematic Instructions
• ADC R
• ADC M
• The contents of register or memory and Carry Flag
(CY) are added to the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair. All flags are modified to reflect
the result of the addition.
CY 1 CY 0
A 50 A 71
B C 20 B C 20
ADC C
D E D E
A=A+R+CY
H L H L
CY 1 CY 0
2050H 30 ADC M 2050H 30
A 20 A 51
A=A+M+CY
H 20 L 50 H 20 L 50
• Example: ADI 10 H
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
A 50 A 60
ADI 10H
A=A+DATA(8)
• Example: ACI 20 H
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
ACI 20H
CY 1 CY 0
A=A+DATA
A 30 A 51
(8)+CY
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
(5) Arithematic Instructions
• Example: DAD D
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
CY 0 CY 0
SP SP
B
D 10
C
E 20
DAD D B
D 10
C
E 20
H 20 L 50 HL=HL+R H 30 L 70
• SUB R
• SUB M
• The contents of the register or memory location are
subtracted from the contents of the accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair.
A 50 A 20
B 30 C B 30 C
D E
SUB B D E
H L A=A-R H L
10
A 50 1020H A 40 1020H 10
H L
SUB M H L
10 20
A=A-M 10 20
(7) Arithematic Instructions
• SBB R
• SBB M
• The contents of the register or memory location and
Borrow Flag (i.e.CY) are subtracted from the contents of the
accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is specified
by H-L pair.
CY 1 CY 0
A 40 A 19
B C 20
SBB C B C 20
D E A=A-R-CY D E
H L H L
CY 1 CY 0
10 10
A 50 2050H A 39 2050H
SBB M
H L H L
20 50 A=A-M-CY 20 50
(8) Arithematic Instructions
• OPERATION: A=A-DATA(8)
• The 8-bit immediate data is subtracted from
the contents of the accumulator.
• The result is stored in accumulator.
• Example: SUI 45 H
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
(9) Arithematic Instructions
• Example: SBI 20 H
CY 1 CY 0
A 50
SBI 20H A 29
A=A-DATA(8)-CY
• INR R
• INR M
• The contents of register or memory location are
incremented by 1.
• The result is stored in the same place.
• If the operand is a memory location, its address
is specified by the contents of H-L pair.
A A
B 10 C INR B B 11 C
D
H
E
L
R=R+1 D
H
E
L
H L 30 H L 31
2050H 2050H
20 50
INR M 20 50
M=M+1
(11) Arithematic Instructions
• INX Rp
• Example: INX H
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
SP SP
B C B C
D E INX H D E
H 10 L 20 H 11 L 21
RP=RP+1
• DCR R
• DCR M
A A
B C B C
D E 20
DCR E D E 19
H L R=R-1 H L
H L
H L 21 20
20 50 2050H
2050H
20 50 DCR M
M=M-1
(13) Arithematic Instructions
• DCX Rp
• Example: DCX D
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
SP SP
B C B C
D 10 E 20 DCX D D 10 E 19
H L H L
RP=RP-1
• ANA R
• ANA M
0101 0101=55H
CY AC 1011 0011=B3H CY 0 AC 1
B3 0001 0001=11H B3
A 55 2050H A 11 2050H
H 20 L 50 ANA M H 20 L 50
A=A and M
(2) Logical Instructions
1011 0011=B3H
0011 1111=3FH
0011 0011=33H
CY AC CY 0 AC 1
ANI 3FH
A B3 A=A and DATA(8) A 33
• Example: XRA C
1010 1010=AAH
BEFORE EXECUTION 0010 1101=2DH AFTER EXECUTION
1000 0111=87H
CY AC CY 0 AC 0
A AA A 87
B 10 C 2D B C 2D
D E
XRA C D E
H L A=A xor R H L
• XRA M
• Example: XRA M
0101 0101=55H
BEFORE EXECUTION 1011 0011=B3H AFTER EXECUTION
1110 0110=E6H
CY AC CY 0 AC 0
B3 XRA M B3
2050H A E6 2050H
A 55
A=A xor M
H 20 L 50 H 20 L 50
CY AC CY 0 AC 0
XRI 39H
A B3 A=A xor DATA(8) A 8A
• ORA Register
• Example: ORA B
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
1010 1010=AAH
0001 0010=12H
BEFORE EXECUTION AFTER EXECUTION
1011 1010=BAH
CY AC CY 0 AC 0
ORA B
A=A or R
A AA A BA
B 12 C B 12 C
D E D E
H L H L
(7) Logical Instructions
• ORA M
• Example: ORA M
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
0101 0101=55H
1011 0011=B3H
BEFORE EXECUTION AFTER EXECUTION
1111 0111=F7H
CY AC CY 0 AC 0
ORA M
A=A or M
B3 B3
A 55 2050H A F7 2050H
H 20 L 50 H 20 L 50
CY AC CY 0 AC 0
ORI 08H
A B3 A=A or DATA(8) A BB
• CMP Register
• CMP M
A B8 A B8
B 10 C CMP D B C
D B9 E A-R D B9 E
H L H L
B8 B8
A B8 2050H A B8 2050H
CMP M
H 20 L 50 A-M H 20 L 50
(10) Logical Instructions
CY Z CY 0 AC 0
CPI 30H
A BA
A-DATA A BA
1011 1010=BAH
• STC
CY 0 CY 1
STC
CY=1
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
(12) Logical Instructions
• CMC
CY 1 CY 0
CMC
• CMA
• RLC
• Rotate accumulator left
• Each binary bit of the accumulator is rotated left
by one position.
• Bit D7 is placed in the position of D0 as well as
in the Carry flag.
• CY is modified according to bit D7.
• Example: RLC.
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION
CY B7 B6 B5 B4 B3 B2 B1 B0
AFTER EXECUTION
B7 B6 B5 B4 B3 B2 B1 B0 B7
• RRC
• Rotate accumulator right
• Each binary bit of the accumulator is rotated right by
one
• position.
• Bit D0 is placed in the position of D7 as well as in the
Carry flag.
• CY is modified according to bit D0.
• Example: RRC.
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION
B7 B6 B5 B4 B3 B2 B1 B0 CY
AFTER EXECUTION
B0 B7 B6 B5 B4 B3 B2 B1 B0
• RAL
• Rotate accumulator left through carry
• Each binary bit of the accumulator is rotated left
by one position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry
flag is placed in the least significant position D0.
• CY is modified according to bit D7.
• Example: RAL.
BEFORE EXECUTION
CY B7 B6 B5 B4 B3 B2 B1 B0
AFTER EXECUTION
B7 B6 B5 B4 B3 B2 B1 B0 CY
• RAR
• Rotate accumulator right through carry
• Each binary bit of the accumulator is rotated left
by one position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry
flag is placed in the least significant position D0.
• CY is modified according to bit D7.
• Example: RAR
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION
B7 B6 B5 B4 B3 B2 B1 B0 CY
AFTER EXECUTION
CY B7 B6 B5 B4 B3 B2 B1 B0
• RET
• Example: RET
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
SP 27FD 00 SP 27FF 00
27FDH 27FDH
PC PC 6200
27FEH 62 27FEH 62
RET
27FFH 27FFH
• Example: RST 6
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
BEFORE EXECUTION AFTER EXECUTION
SP-1
SP 3000 SP 2999 01
2FFEH 2FFEH
PC 2000 PC 0030
2FFFH 20
RST 6 2FFFH
3000H 3000H
RST 0 0*8=0000H
RST 1 0*8=0008H
RST 2 0*8=0010H
RST 3 0*8=0018H
RST 4 0*8=0020H
RST 5 0*8=0028H
RST 6 0*8=0030H
Rst 7 0*8=0038H
(1) Control Instructions
• NOP
• No operation
• No operation is performed.
• The instruction is fetched and decoded but no
operation is executed.
• Example: NOP
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
(2) Control Instructions
• HLT
• Halt
• The CPU finishes executing the current
instruction and halts any further execution.
• An interrupt or reset is necessary to exit from
the halt state.
• Example: HLT
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
(3) Control Instructions
• RIM
• Example: RIM
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)
RIM INSTRUCTION
• SIM
• Example: SIM
SIM Instruction
”Tech_Guru Swapnil
Kaware”
(Thanks For Watching)
Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)