Fully Reused VLSI Architecture Of FMO/Manchester Encoding

using SOLS Technique for DSRC Applications

Guided By:
C.ASHOK KUMAR
Professor,Dept of ECE
BY: A.ANUSHA
148R1D5701
M.Tech 1stYear
VLSIsystemDesign
 Contents
 Objective
 Introduction
 Existing system
 DSRC overview
 Sols
 Systematic Architecture of DSRC Transceiver
 Proposed system
 Advantages
 Additional uses
 Current applications
 Result analysis
 Tool used
 Conclusion
OBJECTIVE
 To develop a high speed Fully Reused
VLSI architecture of FMO and
Manchester encoding .
 This hardware architecture is conducted
from Manchester code and is realized into
FPGA prototyping system.
Introduction
 Provides information about DSRC and
includes important technical details about
5.9GHz DSRC channel allocations.
Existing System
• A short to medium range communications service

• Older DSRC systems such as toll tags operate in the 900

MHz spectrum
– No standard, several proprietary systems are in place

• FCC has authorized 75 MHz of spectrum from 5.850 to

5.925 GHz for DSRC (incl. Canada and Mexico)
– Standardization, Interoperability
– Europe and Japan use the 5.8 GHz spectrum
DSRC Overview
• Supports both Public Safety and Private
operations
• Both roadside to vehicle and vehicle to vehicle
communication environments
• Meant to be a complement to cellular
communications
– provides very high data transfer rates and minimal
latency
– Range – up to 1000 m
– Data Rate – 6 to 27 Mbps
SOLS
•The DSRC standards generally adopt FM0 and
Manchester codes to reach dc-balance
•The coding diversity between the FM0 and
Manchester codes seriously limits the potential
of Hardware Utilization.
Systematic Architecture of DSRC
Transceiver
PROPOSED SYSTEM
 This literature proposes VLSI architecture
of optical communications and uses
CMOS inverter and gated inverter.
 This hardware architecture is conducted
from FSM of Manchester code and is
realized in FPGA prototyping system.
ADVANTAGES
 The encoding capability of this project can
fully support the DSRC standards of
America, Europe, and Japan.
 Used for Intelligent Transport System
Current Applications
 Unlicensed
 Toll collections
 Garage door openers
 CVO (commercial vehicle operations)
Additional Uses
 Office Automation
 Library Automation
 College Automation
 Super Market Automation
 LOS (Line Of Sight Communication)
TOOLS USED
 Xilinx ISE

 Compile and implement the Verilog design

file(s)

 Create the test vectors and simulate the

design
Result analysis
 The SOLS Technique eliminates the
limitation on hardware utilization by 2
important Techniques.
 Using Compact Area Retiming , the
number of transistor is reduced as 22.
 Using Logic Operation Sharing , the HUR
was acheived as 100%.
Conclusion

 The coding diversity between FMO and

manchester encodings seriously limits the
potential to design fully VLSI
architecture design.