Leakage Compensation Design

for SRAM
Presented by

Keerthi Sagar
180942008

Department of Electronics and Communication Engineering

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Introduction
• RAM- Memory where in data can be stored and retrieved in non-sequential
order.
• SRAM occupies major portion of SoC area
• Power Consumption is high
• SRAM is used as cache due to it’s high speed.

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SRAM Design approaches

• Sense Amplifier
• During a read operation, the sense
amplifier predetermines the output
result by sensing the differential current
on two bitlines.
• Since the CMOS technology has been
scaled down very fast, the bitline
capacitances may be too large to drive.

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Current Compensation Circuit

• When the SRAM begins to work, the

current compensation circuit detects the
leakage current of each bit line.
• Then injects a proper current into the
corresponding bit line

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6T SRAM disadvantages
• As the technology evolving toward the nano-meter scale,
• Leakage current increases
• Frequency of operation decreases
• Power consumption increases
• Possibility of Status flip

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Single Ended Load less 5T SRAM

Fig: Schematic of a 5T SRAM cell.

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 5T SRAM contd.
• High Vth PMOS transistors are used, consisting of latch like
storage.
• Low Vth NMOS transistors are used access switches for
driving the bit line.
• An additional NMOS is used which is controlled by word line
(WL) to access Qb.
• The SRAM cell has no path to ground on nodes Q and Qb,
self-refreshing path neutralizes the leakage.
• Eight SRAM cells are coupled with a shared inverter.

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Read Access

Step 1: When clk rises high, the

predischarge is then pulled high to
discharge BLB to ensure that the
parasitic capacitance on BLB would
not be charged back to the SRAM
cell.

Step 2: After discharging BLB, WL

and WE/RD are pulled high to turn
ON N3 and N2, respectively.
Meanwhile, the state of Qb will be
coupled to BLB.

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Write Access

Step 1: When clk rises high, the

predischarge is pulled high to discharge
BLB.

Step 2: If data_in is logic 1 (or 0), WL and

WE/RD (or WE/RD) are high to turn ON
N3 and N2 (or N1), respectively.
Meanwhile, the state of Qb (or Q) will be
coupled to BLB, so that it will be
overwritten.

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Leakage Current Sensor

Fig: Schematics of leakage current sensor and compensation circuit.

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Leakage Current Sensor contd.

• Compensation design is composed of the leakage current

sensor and compensation circuit.
• Leakage current sensor consists of an SRAM cell model and a
comparator.
• SRAM cell model is used as a leakage monitor generating a
voltage proportional to the leakage current, v_leakage, for
comparator.
• If v_leakage is higher than v_ref, comparator will notify a
warning signal to activate the following compensation circuit.

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Comparator

Fig: Schematics of comparator.

This is a differential comparator to compare v_leakage

with a predefined reference voltage, v_ref.

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Read Delay Compensation

• Step 1: v_leakage rises to indicate that the SRAM cell model is

suffered from leakage currents.

• Step 2: Once if v_leakage is higher than v_ref, comparator pulls low

the warning signal.

• Step 3: As soon as the warning drops, P7 in compensation circuit is

turned ON to pull-up BLb such that BL drops fast. In other words, a
positive feedback is used to speed up the read access.

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Read Delay Compensation contd.
• The leakage will slow down the entire read
access, especially in the scenario of state 0
is to be read.
• The compensation circuit speeds up the
read operation.
• The BLb will be predischarged at the
beginning of each read operation.
• Compensate operation only operates, while
data bit 0 is accessed.
CBLb ×VDD
• Charging time, t ch =
iMP
• where tch is the charging time, CBLb is the
equivalent capacitance on BLb, iMP is the
charging current generated by P7 and P8,
and VDD is the system voltage.
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Read Delay Compensation contd.
• The equivalent capacitance on BLb,
• CBLb = 7 · Cload + Cinv + Cpre
• The compensation circuit should not interfere the normal
Read/Write operation
• The charging time is designed to be ten times smaller than the
system clock period.
1
• iMP = CBLb × VDD ×
10×f
• Where f is the frequency of the system clock.

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Implementation and Measurements

• Dynamic Noise Margin

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• Static Noise Margin

The Noise Margins are ∼0.3 V, which means that the state of the stored bit will
not be interfered as long as the amplitude of the noise is lower than 0.3 V.

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Read Delay Measurements

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Read Delay Measurements contd.

Fig: Read delay compensation Results for 0.6v

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Read Delay Measurements contd.

• When SRAM cells are suffered from leakages, the

compensation circuit will be activated to compensate the delay
during read 0 access.
• data_out is the output of the uncompensated SRAM array, and
data_out_t is compensated by the compensation circuit.
• data_out_t is 96.7 ns faster than data_out at 0.6v system
voltage.

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Read Delay Measurements contd.

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Performance Comparison

Technology 40nm 40nm

Cell Architecture 8T 5T
Frequency - 54MHz
Energy/access 8.8pJ 0.9411pJ
Energy/bit 550fJ/bit 188.2fJ/bit
Core area 89*252*64 um2 136.51 *181.16um2
Area/Cap. 1.37um2/bit 4.83um2/bit

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References
• [1] Chua-Chin Wang, Deng-Shain Wang, Chiang-Hsiang Liao, and Sih-Yu Chen,
“A Leakage Compensation Design for Low Supply Voltage SRAM”, IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 5, May 2016.

• [2] A.-T. Do, Z.-H. Kong, K.-S. Yeo, and J. Y. S. Low, “Design and sensitivity
analysis of a new current-mode sense amplifier for low-power SRAM,” IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19,no. 2, pp. 196–204, Feb. 2011.

• [3] H. Xu, S. Jia, Y. Chen, and G. Du, “A current mode sense amplifier with self-
compensation circuit for SRAM application,” in Proc. IEEE 10th Int. Conf. ASIC,
Oct. 2013, pp. 1–4.

• [4] L. Ruixing, B. Na, L. Baitao, Z. Jiafeng, and W. Xiulong, “Bitline leakage

current compensation circuit for high-performance SRAM design,” in Proc. IEEE
7th Int. Conf. Netw., Archit. Storage, Jun. 2012, pp. 109–113.

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Thank you

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