Architectural Classification

ARCHITECTURE CLASSIFICATION :

Three computer architecture classification

presented here
• Flynn’s classification(1966) is based on
multiplicity of instruction and data stream.
• Feng’s classification(1972) is based on serial
versus parallel processing.
• Handler’s classification(1977) is based on
degree of parallelism and pipelining in various
subsystem.

2
 Flynn’s classification :
• It is based upon how the computer relates its
instructions to the data being processed.

• SISD – Single Instruction, Single Data

• SIMD – Single Instruction, Multiple Data

• MISD – Multiple Instruction, Single Data

• MIMD – Multiple Instruction, Multiple Data

3
Flynn’s Classical Taxonomy:
SISD

4
5
Flynn’s Classical Taxonomy:
SIMD

6
7
Flynn’s Classical Taxonomy:
MISD
• Different instructions operated on a single
data element.

• Example: Multiple cryptography algorithms

attempting to crack a single coded
message.

8
 Flynn’s Classical Taxonomy:
MIMD
• Can execute different instructions on
different data elements.
• Most common type of parallel computer.

9
10
 FENG’S CLASSIFICATION
• Tse-yun Feng suggested the use of degree of
parallelism to classify various computer architectures.
• The maximum number of binary digits that can be
processed within a unit time by a computer system is
called the maximum parallelism degree P.
• Let us Pi be the number of bits that can be processed
within the ith processor cycle. Consider processor
cycles indexed by i=1,2,3…,T.
• The average degree of parallelism, Pa is given by

11
 FENG’S CLASSIFICATION:
• In general, Pi ≤ P. We define the utilization rate μ of a
computer system within T cycles is,

• If the computing power is fully utilized (or the parallelism

is fully exploited),we have Pi=P for all i and μ=1 for 100
percent utilization. The utilization rate depends on the
application program being executed.

12
 Feng’s Classification

16K •MPP
(1,16384)
256 •STARAN •PEPE
bit slice (1,256) (32,288)
Length(m) •IlliacIV
64
(64,64)

16 •C.mmP

1 •PDP11 •IBM370 •CRAY-1(64,1)

1 16 32 64
word length (n)

13
• The maximum degree of parallelism P of a computer
system C i.e. P(C) is given by the product of the number
of bits in a word(n) and number of words in parallel(m).

• Word Serial and Bit Serial (WSBS)

• Word Parallel and Bit Serial (WPBS)
• Word Serial and Bit Parallel(WSBP)
• Word Parallel and Bit Parallel (WPBP)

14
 Classification based on sequential
and parallel operation at bit and
word levels :
• WSBS(n=1, m=1) has been called bit parallel
processing because one bit is processed at a time.
• WPBS(n=1, m>1) has been called bit slice processing
because m-bit slice is processes at a time.
• WSBP(n>1, m=1) is found in most existing computers
and has been called as Word Slice processing
because one word of n bit processed at a time.
• WPBP(n>1, m>1) is known as fully parallel processing
in which an array on n x m bits is processes at one time.

15
16
 Händler’s Classification
• Wolfgang Handler has proposed a classification
scheme for identifying the parallelism degree and
pipelining degree built into the hardware structure of
a computer system. He considers at three
subsystem levels:
• Processor Control Unit (PCU)
• Arithmetic Logic Unit (ALU)
• Bit Level Circuit (BLC)
• Each PCU corresponds to one processor or one
CPU. The ALU is equivalent to Processor Element
(PE). The BLC corresponds to combinational logic
circuitry needed to perform 1 bit operations in the
ALU.

slide 17
 Händler’s Classification

• Handler's classification uses the following three pairs of

integers to describe a computer:
• Computer = (p * p', a * a', b * b')
• Where p = number of PCUs
• Where p'= number of PCUs that can be pipelined
• Where a = number of ALUs controlled by each PCU
• Where a'= number of ALUs that can be pipelined
• Where b = number of bits in ALU or processing element
(PE) word
• Where b'= number of pipeline segments on all ALUs or in
a single PE

18
 Händler’s Classification
The following rules and operators are used to show the
relationship between various elements of the
computer:
• The '*' operator is used to indicate that the units are
pipelined or macro-pipelined with a stream of data
running through all the units.
• The '+' operator is used to indicate that the units are not
pipelined but work on independent streams of data.
• The '~' symbol is used to indicate a range of values for
any one of the parameters.
• Peripheral processors are shown before the main
processor using another three pairs of integers. If the
value of the second element of any pair is 1, it may slide 19
omitted for brevity.