M.

Tech Project Presentation

on
Design And Implementation Of FIR Filter Based On Dual
Quality Compressor Based Multipliers With MFA

By
A.Gowthami Under the guidance of
17911D5702 S. Upender
VLSI System Design Associate professor

Dept. Of Electronics and Communication Engineering, VJIT, Hyderabad,

India
CONTENTS

 Introduction
 Literature review
 Objectives
 Tools used
 References
 Conclusion
 Introduction

 In this paper, we propose four 4:2 compressors, which have the

flexibility of switching between the exact and approximate
operating modes.

 Multiplication is basic function in arithmetic operations.

Multiplication based operations such as multiply and Accumulate
unit (MAC), convolution, Fast Fourier Transform (FFT), filtering
(FIR) are widely used in signal processing applications.

 As, multiplication dominates the execution time of DSP systems,

there is need to develop high speed multipliers.
4:2 Compressor

4:2 Structure
 Truth Table of 4:2 Compressor

Inputs Outputs
Cin X4 X3 X2 X1 C out Carry Sum
0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 0
0 0 0 1 0 0 0 1
 Approximate Part & Overall Structure of DQ4:2C1

The approximate output carry is directly connected to the input

X4&Sum is directly connected to X1

In the approximate part of this structure is considerably Fast and Slow

power
 Approximate part of overall Structure of DQ4:2C2

In The Second structure of DQ4:2C2 compound with DQ2:2C1.

The output count generated by connecting it directly to the input X3 in the

approximate part.
 Structure DQ4:2C3

Module: (Sum, Carry, X1,X2,X3,X4);

Input X1, X2, X3, X4
Output Sum, Carry
Wire [2:1] W;
Xnor X1[w[1], X1, X2];
Xnor X2[w[2], X3, X4];
Nand X3[Sum, w [1],w[2]
Assign carrry = X4;
End module
 STRUCTURE DQ4:2C4

Module (Sum, Carry, X1, X2, X3, X4)

Input X1, X2, X3, X4;
Output Sum, Carry;
Wire (A:1) W
Nand a1 [w[1], x1,X2];
Nand a2[w[2], X3, X4];
XNor a3[w[3], X1,X2];
XNor a4[w[4], X3, X4];
Nand a5[carry, w[1], w[2];
Nand a6[Sum, w[3], w[4];
End Module
8 Bit Dadda Multiplier
 Operation

 Dadda multipliers realized by the proposed compressors is studied. Utilised

a better tradeoff between the accuracy and design parameters.

 As an option, the use of both DQ4:2C1 and DQ4:2C4 for the LSB and MSB
parts in the multiplication, respectively, is suggested here. The results for
this multiplier are denoted by DQ4:2Cmixed.

 These multipliers are compared by the approximate Dadda multipliers

implemented by two prior proposed approximate4:2 compressors.
 Modified Full adder (MFA)

MFA is used to two Multiplexers used to reduced area as well as

reduced power,
then compare to Full adder
Proposed System Block Diagram
Operation Proposed Method

 While there are many works in designing approximate multipliers

research efforts on accuracy configurable approximate multipliers
are limited. In this section, we review some of these works

 A static segment method (SSM)is presented, which performs the

multiplication operation
 Literature Review
S.No Authors Journal/ Title Main
conference outcomes
1 P.Kulkarni,and P.Gupta,and International conference of Trading accuracy for  In this paper A
EM.Ercegovac VLSI Design, Jan. 2011, power with an simple correction
pp. 346-351. underdesigned mechanism is
multiplier proposed for usage in
architecture a critical mode, when
correctness of output
is needed. We show
that for inaccurate
multipliers
introducing errors via
partial products is
more promising than
via the adders. We
also show that both of
these approaches
afford a better
tradeoff (of power vs.
accuracy) than bit-
width truncation
2 D.Bran,M.Aktan, and International. Symposium. Multiplier structure In this paper, it is
V.G.Voklobdzija. Crcuits system. for low power shown that the
(ISCA), May 2011, pp. applications in cmos parallel multipliers
3. S.Hashemi, R.I. International A Dynamic range unbiased this paper we propose d
Bahar, and Conference. Comput.- multiplier for approximate a dynamic range
S.Reda. Aided Design (ICCDA), applications unbiased multiplier for
Austin, TX, USA, Nov. approximate
2015, pp. 418-425 applications . Our
design os highly
scalable, enabling
designers to configure it
to trade power and
accuracy as desired .
Unbiased nature leads to
reduction of errors
when used for
computations within
application.
4. C.Liu,J.Han, and Conference. Design, Autom. A Low power, high . This paper focuses on
F.Lombardi, Test Eur. (DATE), 2014,Art. performance approximate the development of error
no. 95. multiplier with configurable analysis techniques for
partial recovery error approximate multipliers,
which are a key hardware
component used in error-
resilient applications, and
presents a novel
algorithm that efficiently
determines the
probability distribution of
the error introduced by
 Tools Required

 CADENCE
 Objectives

 It is used in digital Applications

 It is used in image processing

 It is used as mac unit

SIMULATION
 Design summery
DEVICE UTILIZATION SUMMARY (ESTIMATED VALUES)

Logic Utilization Used Available Utilization

Number of slices 68 14752 0%

Number of 4 Inputs LUTS 118 29504 0%

Number of bonded IOBS 32 250 12%

 
 References

 [1] P. Kulkarni, P. Gupta, and M. Ercegovac, “Trading accuracy for power with an underdesigned multiplier
architecture,” in Proc. 24th Int. Conf. VLSI Design, Jan. 2011, pp. 346–351.

 [2] D. Baran, M. Aktan, and V. G. Oklobdzija, “Multiplier structures for low power applications in deep-
CMOS,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2011, pp. 1061–1064.

 [3] S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. S. Kim, “Energy-efficient approximate

multiplication for digital signal processing and classification applications,” IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 23, no. 6, pp. 1180–1184, Jun. 2015.

 [4] S. Hashemi, R. I. Bahar, and S. Reda, “DRUM: A dynamic range unbiased multiplier for approximate
applications,” in Proc. IEEE/ACM Int.Conf. Comput.-Aided Design (ICCAD), Austin, TX, USA, Nov. 2015,pp.
418–425.

 [5] K. Y. Kyaw, W. L. Goh, and K. S. Yeo, “Low-power high-speed multiplier for error-tolerant application,”
in Proc. IEEE Int. Conf. Electron Devices Solid-State Circuits (EDSSC), Dec. 2010, pp. 1–4.
 [6] H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas, “Bio-inspired imprecise
computational blocks for efficient VLSI implementation of soft-computing applications,” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 4, pp. 850–862, Apr. 2010.
 [7] B. A. Momeni, J. Han, P. Montuschi, and F. Lombardi, “Design and analysis of
approximate compressors for multiplication,” IEEE Trans. Comput., vol. 64, no. 4, pp. 984–
994, Apr. 2015.
 [8] C. H. Lin and I. C. Lin, “High accuracy approximate multiplier with error correction,” in
Proc. EEE 31st Int. Conf. Comput. Design (ICCD), Oct. 2013, pp. 33–38.

 [9] C. Liu, J. Han, and F. Lombardi, “A low-power, high-performance approximate multiplier

with configurable partial error recovery,” in Proc.Conf. Design, Autom. Test Eur. (DATE), 2014,
Art. no. 95.

 [10] C. H. Chang, J. Gu, and M. Zhang, “Ultra low-voltage low-power CMOS 4-2 and 5-2
compressors for fast arithmetic circuits,” IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 51, no.
10, pp. 1985–1997, Oct. 2004
 CONCLUSION

 In this paper, we presented four DQ4:2Cs, which had the

 flexibility of switching between the exact and approximate operating
modes.
 These compressors were employed in the structure ofa 32-bit Dadda
multiplier to provide a configurable multiplier whose accuracy (as well as
its power and speed) could be changed dynamically during the runtime.
THANK YOU