AMBA APB v2.

0 (APB4)
AMBA Overview
 AMBA (Advanced Microcontroller Bus Architecture) is an open standard,
on-chip interconnect for the connection and management of functional
blocks in SoC (System-on-Chip) designs.
 It facilitates multi-processor designs with large number of controllers and
peripherals along with the bus architecture.
 The first AMBA buses were ASB(Advanced System Bus) and APB(Advanced
Peripheral Bus).
 It was first introduced by ARM in 1996.
 AMBA 2 was introduced in 1999 which contained AHB(Advanced High
performance Bus).
 In 2003, ARM introduced AMBA 3 including AXI(Advanced Extensible
interface) and ATB(Advanced Trace Bus).
 In 2010, AMBA 4 specifications were introduced that included AMBA 4 AXI4.
 In 2013, AMBA 5 CHI (Coherent Hub Interface) was introduced to reach
even higher performance and reduce the congestion.
AMBA Bus Implementation
Following diagram represents traditional AMBA based SoC design.
Introduction to APB
 APB (Advanced Peripheral Bus) defines an interface that is optimized for
minimal power consumption.
 It reduces the complexity of interface.
 It is not pipelined.
 The entire transaction is timed at rising edge of clock.
 Every transition will take atleast two clock cycles.
 APB can interface with:
1.) AMBA AHB
2.) AMBA AHB-lite
3.) AMBA AXI
4.) AMBA AXI-lite
 This bus has an address and data phase similar to AHB but with less
complexity (for example no bursts).
APB Revisions
 APB specification introduced in 1998, is now outdated and is replaced by
following three revisions:
 AMBA 2 APB Specification.
 AMBA 3 APB Protocol Specification v1.0
 AMBA APB Protocol Specification v2.0

 AMBA 2 APB Specification.

 It defines interface signals, read and write transfers, and the two APB
components APB Bridge(Master) and APB Slave.
 This version of specification is referred to as APB2.
 AMBA 3 APB Protocol Specification v1.0.
 It defines following additional functionalities:
=> Wait states.
=> Error reporting.
 Following signals were introduced to support such functionalities:
=> PREADY : Indicates completion of an APB transfer.
=> PSLVERR: Indicates failure of a transfer.
 This version of specification is referred to as APB3.

 AMBA APB Protocol Specification v2.0.

 It defines following additional functionalities:
=> Transaction protection.
=> Sparse data transfer.
 Following signals were introduced to support such functionalities:
=> PPROT: A protection signal to support both non-secure and secure transactions on APB.
=> PSTRB: A write strobe signal to enable sparse data transfer on the write data bus.
 This version of specification is referred to as APB4.
 Signal descriptions
Signal Source Description
PCLK Clock source Clock. All the transitions are timed on rising edge of clock.
PRESETn System Bus Reset. For APB reset is an active LOW signal.
Equivalent
PADDR APB Bridge Address. It can be upto 32 bits wide and is driven by peripheral bus bridge unit.
PPROT APB Bridge Protection type. It indicates normal, privileged or secure protection level of
transaction whether the transaction is data access or instruction access.
PSELx APB Bridge Select. The APB bridge unit generates this signal to each peripheral bus slave.
It indicates that the slave device is selected and that a data transfer is required.
There is a PSELx signal for each slave.
PENABLE APB Bridge Enable. This signal indicates the second and subsequent cycles of an APB
transfer.
PWRITE APB Bridge Direction. This signal indicates an APB write access when HIGH and an APB
read access when LOW.
PWDATA APB Bridge Write data. This bus is driven by the peripheral bus bridge unit during write
cycles when PWRITE is HIGH. This bus can be up to 32 bits wide
 Transfers
 APB consists of two types of transfers:

 Write transfer:
 With no wait states.
 With wait states.

 Read transfer:
 With no wait states.
 With wait states.
• Write Transfer:
Below figure shows the write transfer with no wait states.
• Write Transfer:

Below figure shows the write transfer with wait states.

• Read Transfer:

Below figure shows the read transfer with no wait states.

• Read transfer:

Below figure shows the read transfer with wait states.

Write strobes

 The write strobe signals, PSTRB, enable sparse data transfer on the
write data bus.
 Each write strobe signal corresponds to one byte of the write data
bus.
 When asserted HIGH, a write strobe indicates that the corresponding
byte lane of the write data bus contains valid information.
 There is one write strobe for each eight bits of the write data bus, so
PSTRB[n] corresponds to PWDATA[(8n + 7):(8n)].
 Note: For read transfers the bus master must drive all bits of PSTRB
LOW.
Error response:
 Signal added for this functionality in the latest version is : PSLVERR
 It indicates failure of an APB transfer which is possible in both read and write
transactions.

 Dependencies:  PSLVERR should only occur in the last cycle when PSEL,
PENABLE and PREADY are high.
 It is recommended to drive PSLVERR low when any of PSEL,
PENABLE and PREADY are low.
 NOTE:  If an error occurs in any of the transaction, change of state in
peripheral might or might not occur so it is completely peripheral specific.
 If error occurs in write transaction, it doesn’t mean the register within the
peripheral is not updated.
 If error occurs in read transaction, it can return invalid data. There is no
requirement for the peripheral to drive all the data bus to 0’s to indicate
read error.
• For write transfer:

Below figure shows the error response for write transfer

• For read transfer:

Below figure shows the error response for read transfer.

Protection unit support
 To support complex system designs, it is often necessary for both the
interconnect and other devices in the system to provide protection against
illegal transactions.
 For the APB interface, this protection is provided by the PPROT[2:0] signals.
 This signal provides three levels of protection:

1.) Normal or privileged, PPROT[0]

 LOW indicates a normal access
 HIGH indicates a privileged access.

 This is used by some masters to indicate their processing mode.

 A privileged processing mode typically has a greater level of access within a
system.
 2.) Secure or Non-secure, PPROT[1]
 LOW indicates a secure access
 HIGH indicates a non-secure access.

 This bit is configured so that when it is HIGH then the transaction is

considered non-secure and when LOW, the transaction is considered as
secure.

3.) Data or Instruction, PPROT[2]

 LOW indicates a data access
 HIGH indicates a instruction access.

 This indication is provided as a hint and is not accurate in all cases.

 For example, where a transaction contains a mix of instruction and data
items. It is recommended that, by default, an access is marked as a data
access unless it is specifically known to be an instruction access.

 The primary use of PPROT is as an identifier for Secure or Non-secure

transactions. It is acceptable to use different interpretations of the PPROT[0]
and PPROT[2] identifiers.
Operating states