Mesh architecture and routing

algorithms

By: Tushar S

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Agenda
• Introduction
• On-chip interconnection technologies
• Buses
• NoCs
• Mesh architecture in details
• Routing algorithms
• Comparison of Routing Algorithms
• Conclusion

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• Introduction
• The objective of this thesis is to study interconnection
network architectures and routing mechanisms suitable for
tile-based many-core processors and accelerators
• we understand interconnection network architectures,
routing mechanism and network per- formance for tile-
based many-core processors and accelerators. To provide
interconnection network for such architectures

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On-chip interconnection technologies
• Interconnection networks can be classified into shared-medium
networks or switched-medium networks
• A shared-medium network transfers data on a network medium (i.e.,
link) shared by all connected nodes, as shown in Figure 1
• Shared bus network falls into this category. On the other hand, a
switch-medium network consists of switch fabrics (routers) and point-
to-point links.

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On-chip interconnection technologies
• On-chip interconnection networks are implemented either
by using buses or NoCs.
• Buses are divided into following categories
• Shared bus
• Hierarchical bus
• Ring bus

PERFECTVIPs CONFIDENTIAL 5
 NoCs topology

No
1. 2 dimension mesh
2. 2 dimension torus
3. H – tree
4. Fat tree

PERFECTVIPs CONFIDENTIAL 6
Mesh topology in details
Summary of NoC topology

a large number of network topologies have been proposed so far. However, those
employed in practical systems are limited to some well-known topologies, such as
2-D mesh and torus, because their grid-based regular arrangements are
considered to match the two- Dimensional VLSI layout.Therefore,we mainly
compare with 2-Dmesh in the rest of this section.

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• Mesh architecture in details
Mesh - the fabric, a 2-dimensional array of half rings forming a system-wide
interconnect grid
Tile - a modular IP block that can be replicated multiple times across a large
grid
Core Tile - a specific kind of tile that incorporates an Intel's x86 core
IMC Tile - a specific kind of tile that incorporates an integrated memory
controller
Caching/Home Agent (CHA) - a unit found inside the core tiles that maintains
the cache coherency between tiles. The CHA also interfaces with the CMS
Converged/Common Mesh Stop (CMS) - A mesh stop station, facilitating the
interface between a tile and the fabric

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• Mesh architecture in details

Fig: General Floorplan

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• Mesh architecture in details

Fig: mesh example

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• Mesh architecture in details

Implementations of Knights Landing

The Xeon Phi many-core processors based on the Knights Landing microarchitecture
were the first ones to utilize the mesh interconnect. In the case of Knights Landing, a
tile actually consisted of a core duplex. The die was arranged as 7 rows by 6 columns
for a total of 42 tiles. Two of the tiles are used for I/O while two additional tiles are for
the IMC tiles, leaving a total of 38 core tiles

Fig: knights landing cms locations and die comp

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• Mesh architecture in details
• Implementations of skylake
The first Intel server and HEDT microprocessors to implement the mesh were
those based on the Skylake server configuration. Skylake came in three
different die configurations.
12 tiles (3x4), 10-core, Low Core Count (LCC)
20 tiles (5x4), 18-core, High Core Count (HCC)
30 tiles (5x6), 28-core, Extreme Core Count (XCC)
In every configuration, there are two core tiles removed and replaced by two
IMC tile on both edges of the die.

skylake (server) cms locations and die comp

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Thank You

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